Altera Nios II C2H Compiler - Manual (Page 15)

Altera Corporation 9.1 1–9
November 2009 Nios II C2H Compiler User Guide
Introduction to the C2H Compiler
System Architecture
Figure 1–1 shows the architecture of a simple Nios II processor system
that includes one hardware accelerator.
Figure 1–1. Example System Topology with Single Hardware Accelerator
SOPC Builder automatically integrates the accelerator logic into the
system as an SOPC Builder component. If there is more than one
accelerator in the system, multiple accelerators appear in SOPC Builder.
Accelerators are separate from the Nios II processor but can access the
same memory devices that the Nios II processor can.
Nios II
Processor
M
Hardware
Accelerator
Data
Memory
S
Arbitrator
Peripherals
S
S
Instruction
M
Data
M M
Control
Arbitrator
S
Instruction
Memory
Avalon
Switch
Fabric
Write Data & Control Path
Read Data
M
S
Avalon Master Port
Avalon Slave Port
MUX
Data
Memory
S