Altera Nios II C2H Compiler User Manual
Page 73

Altera Corporation
9.1
3–33
November 2009
Nios II C2H Compiler User Guide
C-to-Hardware Mapping Reference
operations that come before it. Because arrays and structures are
equivalent to pointer operations, the same considerations apply when
indexing into an array or structures.
This section describes the implications of aliasing on the C2H Compiler
and outlines methods to prevent unnecessary dependencies.
shows the dependency graph for
Example 3–27. Pointer Aliasing
void foo(int *ptr_a, int *ptr_b)
{
int a, b;
a = *ptr_a;
*ptr_a = a + 7;
b = *ptr_b;
*ptr_b = b + 8;
}
Figure 3–14. Pointer-Related Data Dependency
In this example, the C2H Compiler cannot determine whether or not
ptr_a
and
ptr_b
ever point to the same address. Therefore, it schedules
conservatively, under the assumption that they do. The dependency
graph shows that the read operation from
ptr_b
depends on the write
operation to
ptr_a
. This is not a dependency on the variable
ptr_a
, but
rather a dependency on a location in memory that is unknown at
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)