Digilent 410-178P-KIT - Manual (Page 15)

Atlys Reference Manual
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(playback) sampling rates can be different. The microphone jack is mono, all other jacks are stereo.
The headphone jack is driven by the audio codec's internal 50mW amplifier. The table below
summarizes the audio signals.
The LM4550 audio codec is compliant to the AC ‘97 v2.1 (Intel) standard and is connected as a
Primary Codec (ID1 = 0, ID0 = 0). The table below
shows the AC ‘97 codec control and data signals.
All signals are LVCMOS33.
Signal Name FPGA Pin Pin Function
AUD-BIT-CLK L13 12.288MHZ serial clock output, driven at one-half the frequency of the
24.576MHz crystal input (XTL_IN).
AUD-SDI T18 Serial Data In (to the FPGA) from the codec. SDI data consists of AC
’97 Link Input frames that contain both configuration and PCM audio
data. SDI data is driven on the rising edge of AUD-BIT-CLK.
AUD-SDO N16 Serial Data Out (to the codec) from the FPGA. SDO data consists of AC
’97 Link Output frames that contain both configuration and DAC audio
data. SDO is sampled by the LM4550 on the falling edge of AUD-BIT-
CLK.
AUD-SYNC U17 AC Link frame marker and Warm Reset. SYNC (input to the codec)
defines AC Link frame boundaries. Each frame lasts 256 periods of
AUD-BIT-CLK. SYNC is normally a 48kHz positive pulse with a duty
cycle of 6.25% (16/256). SYNC is sampled on the rising edge of AUD-
BIT-CLK, and the codec takes the first positive sample of SYNC as
defining the start of a new AC Link frame. If a subsequent SYNC pulse
occurs within 255 AUD-BIT-CLK periods of the frame start it will be
ignored. SYNC is also used as an active high input to perform an
(asynchronous) Warm Reset. Warm Reset is used to clear a power-
down state on the codec AC Link interface.
AUD-RESET T17 Cold Reset. This active low signal causes a hardware reset which
returns the control registers and all internal circuits to their default
conditions. RESET must be used to initialize the LM4550 after Power
On when the supplies have stabilized. RESET also clears the codec
from both ATE and Vendor test modes. In addition, while active, it
switches the PC_BEEP mono input directly to both channels of the
LINE_OUT stereo output.
The EDK reference design (available on the Digilent website) leverages our custom AC-97 pcore to
accomplish several standard audio processing tasks such as recording and playing back audio data.
Oscillators/Clocks
The Atlys board includes a single 100MHz CMOS oscillator connected to pin L15 (L15 is a GCLK
input in bank 1). The input clock can drive any or all of the four clock management tiles in the Spartan-
6. Each tile includes two Digital Clock Managers (DCMs) and four Phase-Locked Loops (PLLs).