Digilent 410-178P-KIT - Manual (Page 14)

Atlys Reference Manual
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LM4550
AC-97
Audio
Codec
MIC In
Line In
Line Out
HdPhn Out SDO
SYNC
BIT-CLK
SDI
Spartan-6
RESET
N16
L13
T18
U17
T17
HDMI Type A Connectors HDMI Type D
Pin/Signal J1: IN J2: Out J3: IN Pin/Signal JA: BiDi
1: D2+ B12 B8 J16 1: HPD JP3 *
2: D2_S GND GND GND 2: RES VCCB2
3: D2- A12 A8 J18 3: D2+ N5
4: D1+ B11 C7 L17 4: D2_S GND
5: D1_S GND GND GND 5: D2- P6
6: D1- A11 A7 L18 6: D1+ T4
7: D0+ G9 D8 K17 7: D1_S GND
8: D0_S GND GND GND 8: D1- V4
9: D0- F9 C8 K18 9: D0+ R3
10: Clk+ D11 B6 H17 10: D0_S GND
11: Clk_S GND GND GND 11: D0- T3
12: Clk- C11 A6 H18 12: Clk+ T9
13: CEC NC 0K to Gnd NC 13: Clk_S GND
14: RES NC NC NC 14: Clk- V9
15: SCL C13 D9 M16 15: CEC VCCB2
16: SDA A13 C9 M18 16: Gnd GND
17: Gnd GND GND GND 17: SCL C13**
18: 5V JP4* 5V JP8 * 18: SCA A13**
19: HPD 1K to 5V NC 1K to 5V 19: 5V JP3
*jumper can disconnect Vdd **shared with J1 I2C signals via jumper JP2
EDK designs can use the xps_tft IP core (and its associated driver) to access the HDMI ports. The
xps_tft core reads video data from the DDR2 memory, and sends it to the HDMI port for display on an
external monitor.
An EDK reference design available on the Digilent website (and included as a part of the User Demo)
displays a gradient color bar on an HDMI-connected monitor. Another second EDK reference design
inputs data from port J3 into onboard DDR2. Data is read from the DDR2 frame buffer and displayed
on port J2. An xps_iic core is included to control the DDC on port J2 (this allows consumer devices to
detect the Atlys).
Audio (AC-97)
The Atlys board includes a National
Semiconductor LM4550
AC ‘97 audio
codec (IC3)
with four 1/8” audio jacks
for line-out (J5), headphone-out (J7),
line-in (J4), and microphone-in (J6).
Audio data at up to 18 bits and
48KHz sampling is supported, and
the audio in (record) and audio out