Ethernet phy – Digilent 410-178P-KIT User Manual
Page 12
Atlys Reference Manual
www.digilentinc.com
page 12 of 22
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design on the Digilent website provides an example of driving the Flash memory from an FPGA-based
design.
A board test/demonstration program is loaded into the SPI Flash during manufacturing. That
configuration, also available on the Digilent webpage, can be used to demonstrate and check all of
the devices and circuits on the Atlys board.
Ethernet PHY
The Atlys board includes a Marvell Alaska Tri-mode PHY (the 88E1111) paired with a Halo HFJ11-
1G01E RJ-45 connector. Both MII and GMII interface modes are supported at 10/100/1000 Mb/s.
Default settings used at power-on or reset are:
MII/GMII mode to copper interface
Auto Negotiation Enabled, advertising all speeds, preferring Slave
MDIO interface selected, PHY MDIO address = 00111
No asymmetric pause, no MAC pause, automatic crossover enabled
Energy detect on cable disabled (Sleep Mode disabled), interrupt polarity LOW
The data sheet for the Marvell PHY is available from Marvell only with a valid NDA. Please contact
Marvell for more PHY-specific information.
EDK-based designs can access the PHY using either the xps_ethernetlite IP core for 10/100 Mbps
designs, or the xps_ll_temac IP core for 10/100/1000 Mbps designs.
See Table
K15
F17
L16
F16
N17
Spartan-6
G13
C17
INT#
RESET#
COL
CRS
RXDV
RXCLK
RXER
GTXCLK
TXCLK
TXER
TXEN
MDIO
8
25MHz
Crystal
MDC
CONFIG
7
0001101
CLK
See Table
C18
L12
K16
G18
H15
RXD
TXD
8
8
Marvell M88E1111
x14
Halo HFJ11
Integrated magnetics
F18
Link/Status
LEDs (x6)
RXD Signals
RXD0: G16
RXD1: H14
RXD2: E16
RXD3: F15
RXD4: F14
RXD5: E18
RXD6: D18
RXD7: D17
TXD Signals
TXD0: H16
TXD1: H13
TXD2: K14
TXD3: K13
TXD4: J13
TXD5: G14
TXD6: H12
TXD7: K12