Digilent 410-279P-KIT - Manual (Page 9)

ZYBO™ FPGA Board Reference Manual
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Page 9 of 26
3 Zynq Configuration
Unlike Xilinx FPGA devices, AP SoC devices such as the Zynq-7010 are designed around the processor, which acts as
a master to the programmable logic fabric and all other on-chip peripherals in the processing system. This causes
the Zynq boot process to be more similar to that of a microcontroller than an FPGA. This process involves the
processor loading and executing a Zynq Boot Image, which includes a First Stage Bootloader (FSBL), a bitstream for
configuring the programmable logic (optional), and a user application.
The boot process is broken into three stages:
Stage 0
After the ZYBO is powered on or the Zynq is reset (in software or by pressing PS-SRST), one of the
processors (CPU0) begins executing an internal piece of read-only code called the BootROM. If and only if
the Zynq was just powered on, the BootROM will first latch the state of the mode pins into the mode
register (the mode pins are attached to JP5 on the ZYBO). If the BootROM is being executed due to a reset
event, then the mode pins are not latched, and the previous state of the mode register is used. This
means that the ZYBO needs a power cycle to register any change in the programming mode jumper (JP5).
Next, the BootROM copies an FSBL from the form of non-volatile memory specified by the mode register
to the 256 KB of internal RAM within the APU (called On-Chip Memory, or OCM). The FSBL must be
wrapped up in a Zynq Boot Image in order for the BootROM to properly copy it. The last thing the
BootROM does is hand off execution to the FSBL in OCM.
Stage 1
During this stage, the FSBL first finishes configuring the PS components, such as the DDR memory
controller. Then, if a bitstream is present in the Zynq Boot Image, it is read and used to configure the PL.
Finally, the user application is loaded into memory from the Zynq Boot Image, and execution is handed off
to it.
Stage 2
The last stage is the execution of the user application that was loaded by the FSBL. This can be any sort of
program, from a simple “Hello World” design, to a Second Stage Boot loader used to boot an operating
system like Linux. For a more thorough explanation of the boot process, refer to Chapter 6 of the Zynq
Technical Reference Manual.
The Zynq Boot Image is created using Vivado and Xilinx Software Development Kit (Xilinx SDK). For a tutorial on
how to build an image using these tools that properly targets the ZYBO, download the ZYBO Base System Design
from the Digilent ZYBO product page and follow the included documentation.
The ZYBO supports three different boot modes: microSD, QSPI Flash, and JTAG. The boot mode is selected using
the Mode jumper (JP5), which affects the state of the Zynq configuration pins after power-on. Figure 4 depicts how
the Zynq configuration pins are connected on the ZYBO. Note that MIO2-MIO8 are shared with the QSPI Flash and
MIO LED, but not pictured in Fig. 4.