Digilent 410-279P-KIT - Manual (Page 26)

ZYBO™ FPGA Board Reference Manual
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
Page 26 of 26
digital converter inside the Zynq (XADC). Any or all pairs in the connector can be configured either as analog input
or digital input-output.
In analog input mode, the voltage on these pins must be limited to 1V peak-to-peak. In digital mode, the regular
VCCO-dependent limits apply. See Xilinx datasheets for more information.
The Dual Analog/Digital Pmod on the ZYBO differs from the rest in the routing of its traces. The eight data signals
are grouped into four pairs, with the pairs routed closely coupled for better analog noise immunity. Pins 1 and 7,
pins 2 and 8, pins 3 and 9, and pins 4 and 10 are paired up. Furthermore, each pair has a partially loaded anti-alias
filter laid out on the PCB. The filter does not have capacitors C94-C97. In designs where such filters are desired, the
capacitors can be manually loaded by the user.
NOTE: The coupled routing and the anti-alias filters might limit the data speeds when used for digital signals.
The XADC core within the Zynq is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS.
Either channel can be driven by any of the auxiliary analog input pairs connected to the JXADC header. The XADC
core is controlled and accessed from the PL via the Dynamic Reconfiguration Port (DRP). The DRP also provides
access to voltage monitors that are present on each of the FPGA’s power rails, and a temperature sensor that is
internal to the FPGA. For more information on using the XADC core, refer to the Xilinx document titled “7 Series
FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter.” It is also
possible to access the XADC core directly using the PS, via the “PS-XADC” interface. This interface is described in
full in chapter 30 of the Zynq Technical Reference Manual.
16.4 High-Speed Pmod
The High-speed Pmods use the standard Pmod connector, but have their data signals routed as impedance
matched differential pairs for maximum switching speeds. They have pads for loading resistors for added
protection, but the ZYBO ships with these loaded as 0-Ohm shunts. With the series resistors shunted, these Pmods
offer no protection against short circuits, but allow for much faster switching speeds. The signals are paired to the
adjacent signals in the same row: pins 1 and 2, pins 3 and 4, pins 7 and 8, and pins 9 and 10.
Traces are routed 100 ohm (+/- 10%) differential.
These connectors should be used only when high speed differential signaling is required or the other Pmods are all
occupied. If used as single-ended, coupled pairs will have significant crosstalk. In applications where this is a
concern, the standard Pmod connector shall be used. Another option would be to ground one of the signals (drive
it low from the FPGA) and use its pair for the signal-ended signal.
Since the High-Speed Pmods have 0-ohm shunts instead of protection resistors, the operator must take precaution
to ensure that they do not cause any shorts.