Digilent 410-279P-KIT - Manual (Page 21)

ZYBO™ FPGA Board Reference Manual
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Page 21 of 26
12 Clock Sources
The ZYBO provides a 50 MHz clock to the Zynq PS_CLK input, which is used to generate the clocks for each of the
PS subsystems. The 50 MHz input allows the processor to operate at a maximum frequency of 650 MHz and the
DDR3 memory controller to operate at a maximum of 525 MHz (1050 Mbps). The ZYBO Base System Design
configures the PS to work properly with this input clock, and should be used as a reference when creating custom
designs.
The PS has a dedicated PLL capable of generating up to four reference clocks, each with settable frequencies, that
can be used to clock custom logic implemented in the PL. Additionally, The ZYBO provides an external 125 MHz
reference clock directly to pin L16 of the PL. The external reference clock allows the PL to be used completely
independently of the PS, which can be useful for simple applications that do not require the processor.
The PL of the Zynq-Z7010 also includes two MMCM’s and two PLL’s that can be used to generate clocks with
precise frequencies and phase relationships. Any of the four PS reference clocks or the 125 MHz external reference
clock can be used as an input to the MMCMs and PLLs. For a full description of the capabilities of the Zynq PL
clocking resources, refer to the “7 Series FPGAs Clocking Resources User Guide” available from Xilinx.
Figure 13 outlines the clocking scheme used on the ZYBO. Note that the reference clock output from the Ethernet
PHY is used as the 125 MHz reference clock to the PL, in order to cut the cost of including a dedicated oscillator for
this purpose. Keep in mind that CLK125 will be disabled when the Ethernet PHY (IC1) is held in hardware reset by
driving the PHYRSTB signal low.
Zynq
L16
PS_CLK
Ethernet PHY (IC1)
CKXTAL1
CLK125
50 MHz Oscillator
(IC22)
OUT
PS
PL
PLL
FCLK_CLK[0:3]
E17
PHYRSTB
3.3V
Figure 13. ZYBO clocking.
13 Basic I/O
The ZYBO board includes four slide switches, four push buttons, and four individual LEDs connected to the Zynq PL,
as shown in Fig. 14. There are also two additional pushbuttons and one LED connected directly to the PS via MIO
pins, also shown in Fig. 14. The pushbuttons and slide switches are connected to the Zynq via series resistors to
prevent damage from inadvertent short circuits (a short circuit could occur if a pin assigned to a pushbutton or
slide switch was inadvertently defined as an output). The pushbuttons are "momentary" switches that normally
generate a low output when they are at rest, and a high output only when they are pressed. Slide switches
generate constant high or low inputs depending on their position.