6 usb uart bridge (serial port) – Digilent 410-279P-KIT User Manual

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ZYBO™ FPGA Board Reference Manual

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Page 12 of 26

The PS incorporates an AXI memory port interface, a DDR controller, the associated PHY, and a dedicated I/O bank.
DDR3 memory interface speeds up to 533 MHz/1066 Mbps are supported

The DDR3 uses 1.5V SSTL-compatible inputs. The two components are organized in a tree topology with a series
termination scheme while keeping traces as short as possible and matched.

ZYBO was routed with 40 ohm (+/-10%) trace impedance for single-ended signals, and differential clock and
strobes set to 80 ohms (+/-10%). A feature called DCI (Digitally Controlled Impedance) is used to match the drive
strength and termination impedance of the PS pins to the trace impedance. On the memory side, each chip
calibrates its on-die termination and drive strength using a 240 ohm resistor on the ZQ pin.

Due to layout reasons, the two lower data byte groups (DQ[0-7], DQ[8-15]) were swapped. To the same effect, the
data bits inside byte groups were swapped as well. These changes are transparent to the user. During the whole
design process the Xilinx PCB guidelines were followed.

Both the memory chips and the PS DDR bank are powered from the 1.5V supply. The mid-point reference of 0.75V
is created with a simple resistor divider and is available to the Zynq as external reference.

For proper operation it is essential that the PS memory controller is configured properly. Settings range from the
actual memory flavor to the board trace delays. For your convenience the board definition file provided on our
website will automatically configure the correct parameters.

For best DDR3 performance, DRAM training is enabled for write leveling, read gate, and read data eye options in
the PS Configuration Tool in Xilinx tools. Training is done dynamically by the controller to account for board delays,
process variations and thermal drift. Optimum starting values for the training process are the board delays
(propagation delays) for certain memory signals.

Board delays are specified for each of the byte groups. These parameters are board-specific and were calculated
from the PCB trace length reports. The DQS to CLK Delay and Board Delay values are calculated specific to the
ZYBO memory interface PCB design.

For more details on memory controller operation, refer to the Xilinx Zynq TRM (ug585).

6 USB UART Bridge (Serial Port)

The ZYBO includes an FTDI FT2232HQ USB-UART bridge (attached to connector J11) that lets you use PC
applications to communicate with the board using standard Windows COM port commands. Free USB-COM port
drivers, available from www.ftdichip.com under the "Virtual Com Port" or VCP heading, convert USB packets to
UART/serial port data. Serial port data is exchanged with the Zynq using a two-wire serial port (TXD/RXD). After the
drivers are installed, I/O commands can be used from the PC directed to the COM port to produce serial data
traffic on the Zynq pins. The port is tied to PS (MIO) pins and can be used in combination with the UART 1
controller. A 3.3V->1.8V voltage level translation interfaces the FT2232 with MIO Bank 501, a process transparent
to the user.

The board definition file takes care of mapping the correct MIO pins to the UART 1 controller and uses the
following default protocol parameters: 115200 baud rate, 1 stop bit, no parity, 8-bit character length.

Maximum actual clock frequency is 525 MHz due to PLL limitation.