Digilent 410-279P-KIT - Manual (Page 23)

ZYBO™ FPGA Board Reference Manual
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Page 23 of 26
The digital interface of the SSM2603 is wired to the programmable logic side of the Zynq. Audio data is transferred
via the I
2 S protocol. Configuration is done over an I 2 C bus. The device address of the SSM2603 is 0011010b. All
digital I/O are 3.3V level and connect to a 3.3V-powered FPGA bank.
SSM2603 pin Protocol Direction (Zynq POW) Zynq pin
BCLK I 2 S (Serial Clock) Output K18
PBDAT I 2 S (Playback Data) Output M17
PBLRC I 2 S (Playback Channel Clock) Output L17
RECDAT I 2 S (Record Data) Input K17
RECLRC I 2 S (Record Channel Clock) Output M18
SDIN I 2 C (Data) Input/Output N17
SCLK I 2 C (Clock) Output N18
MUTE Digital Enable (Active Low) Output P18
MCLK Master Clock Output T19
Table 8. Digital audio signals, with the SSM2603 in default slave mode.
The audio codec needs to be clocked from the Zynq on the MCLK pin. This master clock will be used by the audio
codec to establish the audio sampling frequency. This clock is required to be an integer multiple of the desired
sampling rate. The default settings require a master clock of 12.288 Mhz, resulting in a 48 kHz sampling rate. For
other frequencies and their respective configuration parameters, consult the SSM2603 datasheet.
The codec has two modes: master and slave, with the slave being default. In this mode, the direction of the signals
is specified in Table 8. When configured as master, the direction of BCLK, PBLRC and RECLRC is inverted. In this
mode, the codec generates the proper frequencies for these clocks. No matter where are the clocks are generated,
PBDAT needs to be driven out and RECDAT sampled in sync with them. The master clock is always driven out of the
Zynq. The timing diagram of an I
2 S stream can be seen on Figure 15. Note the one-cycle delay of the data stream
with respect to the left/right clock changing state. Audio samples are transmitted MSB first, noted as 1 in the
diagram.
PB/RECLRC
BCLK
PB/RECDAT
1/f
s
N 1 2 3 N 1 2 3 N
Figure 15. I 2 S timing diagram.
The digital mute signal (MUTE) is active-low, with a pull-down resistor. This means that when not used in the
design, it will stay low and the analog outputs of the codec will stay muted. To enable the analog outputs, drive
this signal high.