Digilent 410-279P-KIT - Manual (Page 16)

ZYBO™ FPGA Board Reference Manual
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Page 16 of 26
MIO bank is powered from 1.8V, the RGMII interface uses 1.8V HSTL Class 1 drivers. For this I/O standard an
external reference of 0.9V is provided in bank 501 (PS_MIO_VREF). Mapping out the correct pins and configuring
the interface is handled by the ZYBO board definition file.
Although the default power-up configuration of the PHY might be enough in most applications, the MDIO bus is
available for management. The RTL8211E-VL is assigned address 00001b. With simple register read and write
commands, status information can be read out or configuration changed. The Realtek PHY follows industry-
standard register map for basic configuration.
The RGMII specification calls for the receive (RXC) and transmit clock (TXC) to be delayed relative to the data
signals (RXD[0:3], RXCTL and TXD[0:3], TXCTL). Xilinx PCB guidelines also require this delay to be added. The
RTL8211E-VL is capable of inserting a 2ns delay on both the TXC and RXC so that board traces do not need to be
made longer.
The PHY is clocked from the same 50 MHz oscillator (IC22) that clocks the PS too. The parasitic capacitance of the
two loads is low enough to be driven from a single source.
On an Ethernet network each node needs a unique MAC address. To this end, a Microchip 24AA02E48 EEPROM is
provided on the ZYBO. On one hand it is a read-writeable EEPROM that can be accessed via I
2 C. On the other hand
it features a read-only memory section that comes pre-programmed with a unique identifier. This unique identifier
can be read and used as a MAC address, avoiding a possible address conflict on the network. The I
2 C interface
connects to the PL side and can be accessed from the PS over EMIO as well. The device address of the EEPROM is
1010000b.
For more information on using the Gigabit Ethernet MAC, refer to the Xilinx Zynq TRM (ug585).
10 HDMI Source/Sink Port
An input and output-capable HDMI Port connects to the programmable logic pins. Over this connector an HDMI or
DVI-compatible video stream can be driven in or out of the ZYBO. Encoding or decoding the HDMI/DVI video
stream needs to be implemented in logic, as well as auxiliary functions, like DDC or CEC. Depending on the actual
design, it can take the Source role driving a monitor/TV display, or behave as a Sink accepting a video stream from
any HDMI/DVI Source, like a laptop or smartphone.
On-board auxiliary buffers and electronic switches control the direction of signals that differ between Source and
Sink. These signals are summarized Table 6.
Signal Role Description Direction (Zynq POW) How to control
HPD
Source Hot-plug detect; signals the
presence of a Sink to a Source Input HDMI_OUT_EN = 1
Sink Output HDMI_OUT_EN = 0
5V0
Source
Auxiliary power for Sink
Output HDMI_OUT_EN = 1
Sink Input HDMI_OUT_EN = 0
Table 6. HDMI signal direction in Source and Sink roles.
The CEC function is bi-directional by definition, so it is treated the same no matter what role the port takes. If the
CEC function is not used, declare it as input and constrain it to the correct PL pin to leave other devices on the CEC
bus unaffected.