Appendix f, Continued), Sample configuration task – Rockwell Automation 57C421B Pulsetach Input Module/DCS 5000/AutoMax User Manual
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FĆ6
Appendix F
(Continued)
Sample Configuration Task
The following is a sample configuration for an input module located in slot 5:
1000
TASK PG_SPEED[ TYPE=CONTROL, PRIORITY=10, SLOT=0 ]
1010
TASK PG_LATCH[ TYPE=BASIC, PRIORITY=10, SLOT=0 ]
1020
TASK PG_COMP[ TYPE=BASIC, PRIORITY=10, SLOT=0 ]
2000
IODEF COUNT_VAL![ SLOT=4, REGISTER=0 ]
2010
IODEF COUNT%[ SLOT=4, REGISTER=1 ]
2020
IODEF TIMER%[ SLOT=4, REGISTER=2 ]
2030
IODEF COMP_VAL![ SLOT=4, REGISTER=3 ]
2040
IODEF LOW_COMP%[ SLOT=4, REGISTER=4 ]
2050
IODEF ISCR%[ SLOT=4, REGISTER=5 ]
2060
IODEF CREG1%[ SLOT=4, REGISTER=6 ]
2070
IODEF CREG2%[ SLOT=4, REGISTER=7 ]
2080
!
2085
!ăREGISTER #5, ISCR
2090
!
3000
IODEF DIS_CLR@[ SLOT=4, REGISTER=5, BIT=14 ]
3010
IODEF TIM_MODE@[ SLOT=4, REGISTER=5, BIT=13 ]
3020
IODEF MULT@[ SLOT=4, REGISTER=5, BIT=12 ]
3030
IODEF EQU_INT@[ SLOT=4, REGISTER=5, BIT=11 ]
3040
IODEF ORG_INT@[ SLOT=4, REGISTER=5, BIT=10 ]
3050
IODEF STP_INT@[ SLOT=4, REGISTER=5, BIT=9 ]
3060
IODEF LAT_INT@[ SLOT=4, REGISTER=5, BIT=8 ]
3070
IODEF CCLK_EN@[ SLOT=4, REGISTER=5, BIT=6 ]
3080
IODEF INT_R@[ SLOT=4, REGISTER=5, BIT=5 ]
3090
IODEF CLR_MOD1@[ SLOT=4, REGISTER=5, BIT=4 ]
3100
IODEF CLR_MOD2@[ SLOT=4, REGISTER=5, BIT=3 ]
3110
!
3120
!ăREGISTER #6
3130
!ă
4000
IODEF RESET@[ SLOT=4, REGISTER=6, BIT=15 ]
4010
IODEF LATCH_POLARITY@[ SLOT=4, REGISTER=6, BIT=14 ]
4020
IODEF ORIGIN_POLARITY@[ SLOT=4, REGISTER=6, BIT=13 ]
4030
IODEF STOP_POLARITY@[ SLOT=4, REGISTER=6, BIT=12 ]
4040
IODEF SINGLE_INPUT@[ SLOT=4, REGISTER=6, BIT=11 ]
4050
IODEF ORIGING_SEL@[ SLOT=4, REGISTER=6, BIT=10 ]
4060
IODEF INHIBIT_CNTR@[ SLOT=4, REGISTER=6, BIT=9 ]
4070
IODEF NMBR_CHANNELS@[ SLOT=4, REGISTER=6, BIT=8 ]
4080
IODEF Z_PULSE_REV@[ SLOT=4, REGISTER=6, BIT=3 ]
4090
IODEF Z_PULSE_FWD@[ SLOT=4, REGISTER=6, BIT=2 ]
4100
IODEF EXT_STOP_EN@[ SLOT=4, REGISTER=6, BIT=1 ]
4110
IODEF EXT_LATCH_EN@[ SLOT=4, REGISTER=6, BIT=0 ]
4120
!
4130
!ăREGISTER #7
4140
!
5000
IODEF ORIGIN_RESET@[ SLOT=4, REGISTER=7, BIT=15 ]
5010
IODEF STOP_RESET@[ SLOT=4, REGISTER=7, BIT=14 ]
5020
IODEF LATCH_RESET@[ SLOT=4, REGISTER=7, BIT=13 ]
5030
IODEF CNTR_EQ_RST@[ SLOT=4, REGISTER=7, BIT=12 ]
5040
IODEF BORROW_RESET@[ SLOT=4, REGISTER=7, BIT=11 ]
5050
IODEF CARRY_RESET@[ SLOT=4, REGISTER=7, BIT=10 ]
5060
IODEF COUNT_DIR@[ SLOT=4, REGISTER=7, BIT=9 ]
5070
IODEF CLOCK_ERROR@[ SLOT=4, REGISTER=7, BIT=8 ]
5080
IODEF EXT_ORG_STATUS@[ SLOT=4, REGISTER=7, BIT=7 ]
5090
IODEF EXT_STOP_STATUS@[ SLOT=4, REGISTER=7, BIT=6 ]
5100
IODEF EXT_LATCH_STATUS@[ SLOT=4, REGISTER=7, BIT=5 ]
5110
IODEF COUNTER_EQ@[ SLOT=4, REGISTER=7, BIT=4 ]
5120
IODEF COUNTER_LT@[ SLOT=4, REGISTER=7, BIT=3 ]
5130
IODEF COUNTER_GT2[ SLOT=4, REGISTER=7, BIT=2 ]
5140
IODEF BORROW_STATUS@[ SLOT=4, REGISTER=7, BIT=1 ]
5150
IODEF CARRY_STATUS@[ SLOT=4, REGISTER=7, BIT=0 ]
32767
END