Rockwell Automation 57C421B Pulsetach Input Module/DCS 5000/AutoMax - Manual (Page 28)

4Ć6
4.2.4 Interrupt Status Control Register (Register 5)
The bits in register 5 are used to enable interrupts and define other
module characteristics. This register is read/write. Refer to figure 4.9.
WARNING
BITS 0, 1, 2, 7, AND 15 ARE CONTROLLED BY THE OPERATING SYSTEM AND
MUST NOT BE WRITTEN TO BY THE USER. WRITING TO THESE BITS MAY
RESULT IN ALL OUTPUTS BEING TURNED OFF AND ALL TASKS IN THE RACK
BEING STOPPED. FAILURE TO OBSERVE THESE PRECAUTIONS COULD
RESULTIN BODILY INJURY.
Bit: 0
Description: System use only.
Bit: 1
Description: System use only.
Bit: 2
Description: System use only.
Bits: 3 and 4
Description: Counter Clear Control
These bits are used to define the conditions under which the
counter is reset to zero.
Bit 3 Bit 4 Condition
0
0
1
1
0
1
0
1
Never clear (1)
External latch (2)
Counter equal comparator
After counter is read (3)
(1) Bit 14 of this register must also be set to one.
(2) The external latch input must also be enabled (register 6, bit 0).
(3) This feature is not available in external latch mode (i.e., register
6, bit 0 = 1).
NOTE: If the module is set up to clear the counter after the counter is
read (bits 3 and 4 = zero), using the Variable Monitor or the I/O
monitor function to monitor register 0 and/or 1 will cause the counter
register to reset.
Bit: 5
Description: Timer Interrupt Enable
When this bit is equal to one (i.e., speed detection mode), the
counter data is latched, an interrupt is generated, and the counter is
reset each time the time period specified in register 2 (Counter
Update Register) expires. (Note that if bit 14 is also set to one, the
counter will not be cleared after an interrupt.)
If the status of bit 5 is changed to zero after the module has been
operating in the speed detection mode, the counter data will be
latched when bit 5 makes the transition from one to zero and the
counter will not be reset.
Bit: 6
Description: Generate CCLK
When this bit is set to one, the module will provide the CCLK signal
to the rack backplane. The CCLK signal can be generated by this
module, an Analog Input module (M/N 57C409), a Resolver Input