Cirrus Logic CS5467 - Manual (Page 27)

CS5467
DS714F3 27
7.6.5 Register Read and Write
Read and Write commands provide access to on-chip registers. After a Read command, the addressed data
can be clocked out the SDO pin by SCLK. After a Write command, 24 bits of write data must follow. The data
is transferred to the addressed register after the 24
th
data bit is received. Registers are organized into pages
of 32 addresses each. To access a desired page, write its number to the Page register at address 31.
W/R Write/Read control
0 = Read
1 = Write
RA[4:0] Register address.
Page 0 Registers
Address RA[4:0] Name Description
0 00000 Config Configuration
1 00001 I1 Instantaneous Current Channel 1
2 00010 V1 Instantaneous Voltage Channel 1
3 00011 P1 Instantaneous Power Channel 1
4 00100 P1
AVG
Active Power Channel 1
5 00101 I1
RMS
RMS Current Channel 1
6 00110 V1
RMS
RMS Voltage Channel 1
7 00111 I2 Instantaneous Current Channel 2
8 01000 V2 Instantaneous Voltage Channel 2
9 01001 P2 Instantaneous Power Channel 2
10 01010 P2
AVG
Active Power Channel 2
11 01011 I2
RMS
RMS Current Channel 2
12 01100 V2
RMS
RMS Voltage Channel 2
13 01101 Q1
AVG
Reactive Power Channel 1
14 01110 Q1 Instantaneous Quadrature Power Channel 1
15 01111 Status Internal Status
16 10000 Q2
AVG
Reactive Power Channel 2
17 10001 Q2 Instantaneous Quadrature Power Channel 2
18 10010 I1
PEAK
Peak Current Channel 1
19 10011 V1
PEAK
Peak Voltage Channel 1
20 10100 S1 Apparent Power Channel 1
21 10101 PF1 Power Factor Channel 1
22 10110 I2
PEAK
Peak Current Channel 2
23 10111 V2
PEAK
Peak Voltage Channel 2
24 11000 S2 Apparent Power Channel 2
25 11001 PF2 Power Factor Channel 2
26 11010 Mask Interrupt Mask
27 11011 T Temperature
28 11100 Ctrl Control
29 11101 E
PULSE
Active Energy Pulse Output
30 11110 S
PULSE
Apparent Energy Pulse Output
31 R 11111 Q
PULSE
Reactive Energy Pulse Output
31 W 11111 Page Register Page Select
Warning: Do not write to unpublished register locations.
B7 B6 B5 B4 B3 B2 B1 B0
0 W/R RA4 RA3 RA2 RA1 RA0 0