Cirrus Logic CS5467 - Manual (Page 10)

CS5467
10 DS714F3
DIGITAL CHARACTERISTICS
• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions .
• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.
• VA+ = VD+ = 5V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.
• DCLK = 4.096 MHz.
Notes: 10. All measurements performed under static conditions.
11. If a crystal is used, XIN frequency must remain between 2.5 MHz - 5.0 MHz. If an external oscillator is
used, XIN frequency range is 2.5 MHz - 20 MHz, but K must be set so that MCLK is between
2.5 MHz - 5.0 MHz.
12. If external MCLK is used, the duty cycle must be between 45% and 55% to maintain this specification.
13. The frequency of CPUCLK is equal to MCLK.
14. The minimum FSCR is limited by the maximum allowed gain register value. The maximum FSCR is
limited by the full-scale signal applied to the input.
15. Configuration register (Config) bits PC[6:0] are set to “0000000”.
16. The MODE pin is pulled low by an internal resistor.
Parameter Symbol Min Typ Max Unit
Master Clock Characteristics
Master Clock Frequency Internal Gate Oscillator (Note 11) DCLK 2.5 4.096 20 MHz
Master Clock Duty Cycle 40 - 60 %
CPUCLK Duty Cycle (Note 12 and 13) 40 - 60 %
Filter Characteristics
Phase Compensation Range (60 Hz, OWR = 4000 Hz) -5.4 - +5.4 °
Input Sampling Rate DCLK = MCLK/K - DCLK/8 - Hz
Digital Filter Output Word Rate (Both channels) OWR - DCLK/1024 - Hz
High-pass Filter Corner Frequency -3 dB - 0.5 - Hz
Full-scale DC Calibration Range (Referred to Input) (Note 14) FSCR 25 - 100 %FS
Channel-to-channel Time-shift Error (Note 15) 1.0 µs
Input/Output Characteristics
High-level Input Voltage
All Pins Except XIN and SCLK and RESET
XIN
SCLK and RESET
V
IH
0.6 VD+
(VD+) – 0.5
0.8
VD+
-
-
- -
-
- V
V
V
Low-level Input Voltage (VD = 5 V)
All Pins Except XIN and SCLK and RESET
XIN
SCLK and RESET
V
IL
-
-
- -
-
- 0.8
1.5
0.2
VD+
V
V
V
Low-level Input Voltage (VD = 3.3 V)
All Pins Except XIN and SCLK and RESET
XIN
SCLK and RESET
V
IL
-
-
- -
-
- 0.48
0.3
0.2
VD+
V
V
V
High-level Output Voltage I
out
= +5 mA V
OH
(VD+) - 1.0 - - V
Low-level Output Voltage
I
out
= -5 mA (VD = +5V)
I
out
= -2.5 mA (VD = +3.3V)
V
OL
-
- -
- 0.4
0.4 V
V
Input Leakage Current (Note 16) I
in
- ±1 ±10 µA
3-state Leakage Current I
OZ
- - ±10 µA
Digital Output Pin Capacitance C
out
- 5 - pF