Cirrus Logic CS1810xx - Manual (Page 47)

CobraNet Hardware User’s Manual
Mechanical Drawings and Schematics
DS651UM23
©
Copyright 2005 Cirrus Logic, Inc. 47
Version 2.3
Figure 27. CM-2 RevF Schematic Page 4 of 7
VCXO_CT
RL
1
MC
LK
_ S E L
2
DBDA 3 DBCK 4
NC
5
NC
6
NC
7
DAO_M
CL
K
8
TEST 9
VDDD 10
HS3
11
NC
12
GND 13
DAO2_L
RCL
K
14
DAO1_DAT
A3
15
DAO1_DAT
A2/HS2
16
DAO1_DAT
A1/HS1
17
VDDIO 18
DAO1_DAT
A0/HS0
19
DAO1_SCL
K
20
GND 21
DAO1_L
RCL
K
22
U
A
R T_
TX
_ O
E
23
VDDD 24
U
A
R T_
TX
D
25
UART
_RXD
26
GND 27
NC 28
VDDIO 33
GND 36
EXT
_W
E#
38
VDDIO 44
GND 47
NC 50
NC 51
NC 52
NC 53
VDDD 54
SD_A12/EXT
_ A11
55
SD_A11/EXT
_ A10
56
GND 57
SD_A9/EXT
_A9
58
SD_A8/EXT
_A8
59
VDDIO 60
SD_A7/EXT
_A7
61
SD_A6/EXT
_A6
62
GND 63
SD_A5/EXT
_A5
64
EXT
_CS2#
65
VDDD 66
SD_A4/EXT
_A4
67
SD_A3/EXT
_A3
68
GND 69
SD_A2/EXT
_A2
70
SD_A1/EXT
_A1
71
SD_A0/EXT
_A0
72
VDDIO 73
SD_A10/EXT
_ A12
74
SD_A14/EXT
_ A13
75
GND 76
SD_A13/EXT
_ A14
77
NC 78
NC 79
NC 80
NC 81
EXT
_A15
82
VDDD 83
EXT
_A16
84
EXT
_A17
85
GND 86
EXT
_A18
87
EXT
_A19
88
EXT
_OE#
89
EXT
_CS1#
90
VDDIO 91
MU
TE
#
92
RESET
#
93
GND 94
W
A
T C
HDOG
_OUT
95
IO
W
A
IT
96
REF
C L K _I
N
97
VDDD 98
GP
IO
0
99
GP
IO
1
100
GND 101
HACK
#
102
HDS#
103
HEN#
104
HADDR3
105
HADDR2
106
HR/W
#
107
GP
IO
2
108
HADDR1
109
HADDR0
110
HDAT
A7
111
HDAT
A6
112
VDDIO 113
HDAT
A5
114
HDAT
A4
115
GND 116
HDAT
A3
117
HDAT
A2
118
VDDD 119
HDAT
A1
120
HDAT
A0
121
GND 122
XT
AL
_OUT
123
XT
I
125
XT
O
124
GND_A 126
FI
L T 2
127
FI
L T 1
128
VDD_A 129
VDDD 130
DAI
1_DAT
A3
131
DAI
1_DAT
A2
132
GND 133
DAI
1_DAT
A1
134
DAI
1_DAT
A0
135
VDDIO 136
DAI
1_SCL
K
137
DAI
1_L
RCL
K
138
GND 139
HREQ#
140
NC
141
NC
142
IR
Q
1
143
IR
Q
2
144
SD_D7/EXT
_ D15
29
SD_D6/EXT
_ D14
30
SD_D5/EXT
_ D13
31
SD_D4/EXT
_ D12
32
SD_D3/EXT
_ D11
34
SD_D2/EXT
_ D10
35
SD_D1/EXT
_D9
37
SD_D0/EXT
_D8
39
SD_D15/EXT
_ D7
40
SD_D14/EXT
_ D6
41
SD_D13/EXT
_ D5
42
SD_D12/EXT
_ D4
43
SD_D11/EXT
_ D3
45
SD_D10/EXT
_ D2
46
SD_D9/EXT
_D1
48
SD_D8/EXT
_D0
49
U6 CS18101
VCC_+
1. 8
VCC_+
3. 3
HRESET
_B
UF
#
OE# WE
#
F L ASH_CS#
M
AC_CS#
IO
W
A IT
DAT
A0
DAT
A1
DAT
A2
DAT
A3
DAT
A4
DAT
A5
DAT
A6
DAT
A7
DAT
A8
DAT
A9
DAT
A10
DAT
A11
DAT
A12
DAT
A13
DAT
A14
DAT
A15
ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19
U
A R T_
TX
D
UART
_RXD
U
A R T_
TX
_ O E
HDAT
A0
HDAT
A1
HDAT
A2
HDAT
A3
HDAT
A4
HDAT
A5
HDAT
A6
HDAT
A7
HADDR0 HADDR1 HADDR2 HADDR3 HRW HDS# HREQ# HACK
#
HEN# M
C L K
_I
NT
ERNAL
FS
1
SSI
_CL
K
SSI
_DI
N
0
SSI
_DI
N
1
SSI
_DI
N
2
SSI
_DI
N
3
SSI
_DOUT
0
SSI
_DOUT
1
SSI
_DOUT
2
SSI
_DOUT
3
RSVD1 RSVD2 RSVD4 RSVD3 VCXO_CT
RL
MA
C
_ IR
Q
0
MA
C
_ IR
Q
1
MC
LK
_ S E L
DAT
A[
0.
.15]
ADDR[
0.
.1
9]
HRESET
_B
UF
#
OE# WE
#
F L ASH_CS#
M
AC_CS#
IO
W
A IT
C41 22 pF
C40 22 pF
SSI
_DOUT
[0
.. 3 ]
SSI
_ DI
N[
0. .3
]
HADDR[
0.
.3 ]
HDAT
A[
0. .7
]
DAT
A[
0.
.1
5]
ADDR[
0.
.1
9]
U
A R T_
TX
_ O E
UART
_RXD
U A
R T_
TX
D
HRW HDS# HEN# HREQ# HACK
#
HADDR[
0. .3
]
HDAT
A[
0.
.7
]
M
C
L K _I
NT
ERNAL
FS
1
SSI
_CL
K
SSI
_DOUT
[0
.. 3 ]
SSI
_ DI
N[
0. .3
]
MC
LK
_ S E L
VCXO_CT
RL
MA
C _ IR
Q
0
MA
C _ IR
Q
1
GP
IO
0
GP
IO
1
G
P IO
[0
..1
]
G P IO
[0
..1
]
REF
CL
K _ IN
W
A
T C HDOG
MU
TE
#
REF
C L K
_I
N
W
A
T C HDOG
MU
TE
#
VCC_+
3 .3
VCC_+
1 .8
VCC_+
1 .8
C24 0.
1 uF
FB
1
F B EAD,
68 Ohm
@
100 M
H
z
C4
10 uF
, X5R,
6.
3 Vo
lt s
C5
10 uF
, X5R,
6.
3 Vo
lt s
VCC_DSPA
R13
R14
3.
3K
Ohm
VCC_+
3.
3
VCC_+
3 .3
GN
D
DEB
UG
_CL
K
DEB
UG
_DAT
A
D
ebug Port
RSVD1 SSI
_DOUT
0
SSI
_DOUT
1
SSI
_DOUT
2
HS0 - Do
wn
HS1 - Up HS2 - Do
wn
HS3 - Do
wn
1
2
3
4 5
6
7
8
CN3 0.
1 uF
, 4x Array
1
2
3
4 5
6
7
8
CN2 0.
1 uF
, 4x Array
VCC_+
3. 3
VCC_+
1. 8
1
2
3
4 5
6
7
8
CN5 0.
1 uF
, 4x Array
1
2
3
4 5
6
7
8
CN4 0.
1 uF
, 4x Array
VCC_+
1.
8
1
2
3
4 5
6
7
8
CN1 0.
1 uF
, 4x Array
GN
D
C43 1000 pF
, COG
R41 5.
90K
Ohm
C42
2.
2 uF
, X7R,
1206
CL
K _ 25
CL
K _ 25
1
2
Y1 25 M
H z
VCC_+
3 .3
SSI
_CL
K
_J
C44 0. 1 uF
R45
24.
9 Ohm
, 1%
VCC_+
3.
3
1
2
3
4 5
6
7
8
CN12 0.
1 uF
, 4x Array
R53
R54
24.
9 Ohm
, 1%
DAO1_L
RCL
K
SSI
_CL
K
_ J
R43
R47
R49
R51 3.
3K
Ohm
R42
R46
R48
R50 3.
3K
Ohm
De
fa
ul
t B
o o t M
o de
:
T h es
e pul
lu
ps and pul
ld
o w
ns are
use
d
to
se
t the
bo
o t m
o de
o
f the
DSP.
T
h e
appro
priate
re
sisto
r is instal
le d to
se
le ct
the
bo
o t m
o de
.
1 2 3 4 JP
1
CON4
R55
1 M
eg
O hm
RSVD[
1.
.5 ]
RSVD[
1. .5
]
RSVD[
1. .5
]
RSVD5
9 10
8
U10C 74L
VC32
GN
D
A/B
1
1A
2
1B
3
1Y
4
2A
5
2B
6
2Y
7
GND 8 3Y
9
3B
10
3A
11
4Y
12
4B
13
4A
14
G
15
VCC 16
U11 74L
VC157
C53 0.
1 uF
VCC_+
3 .3
VCC_+
3. 3
C52 0. 1 uF
D1 1N4148W
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
DAO2_L
RCL
K
DAO1_L
RCL
K
DAO2_L
RCL
K
R57 10K
Ohm
R56
3.3K Ohm
DAO1_L
RCL
K