Rainbow Electronics MAX1464 - Manual (Page 22)

MAX1464
Low-Power, Low-Noise Multichannel
Sensor Signal Processor
22 ______________________________________________________________________________________
Program and Coefficient Memory
The program and coefficient memory, FLASH partition 0,
is addressed by the CPU and by the serial interface
sequentially from 0000h (0 dec) to 0FFFh (4095 dec).
Program execution by the CPU always begins at address
0000h and proceeds toward 0FFFh in 1-byte increments.
Although both the CPU and the serial interface can
address a 16-bit field, the FLASH size only uses 12
bits. Therefore, the leading 4 MSBs of the address field
are ignored. It is advisable to have all leading bits of
the 16-bit address in PFAR[15:0] set to zero.
The FLASH memory in partition 0 can be erased in indi-
vidual 64-byte pages using the page-erase command,
or erased in bulk using the all-erase command. The
information data memory (partition 1) is unaffected by
any operation performed on partition 0.
Information Data Memory
The information data memory, FLASH partition 1, is
addressed by bytes sequentially from 00h (0 dec) to 7Fh
(127 dec). The addressed byte should have all leading
bits of the 16-bit address in PFAR[15:0] set to zero.
The FLASH memory in partition 1 has only two 64-byte
pages that can be erased separately using the page-
erase command, or erased together using the all-erase
command. Data in partition 0 is not affected by any
operation performed on partition 1.
MAX1464 CPU Instruction Set
The MAX1464 CPU has 16 instructions used to perform
all calculations for sensor compensation, linearization,
and signal output functions. Each instruction comprises
a 4-bit op code and a 4-bit CPU register address. The
op code describes what operation to perform; the reg-
ister address describes what register, or registers, to
perform the operation on.
Instruction Format
All instructions are single-byte instructions with the
exception of load data from instruction memory. LDX
fetches the 2 following bytes of instruction memory and
loads them into a register. This is how calibration and
compensation coefficients are stored within the
MAX1464. Any number of coefficients can be stored in
instruction memory. The instruction code format is as
follows:
Instruction Set Details
LDX Load Register X
Op-code: 0000 XXXX BINARY 0Xh
Operation:
X-register ← [PC+1] : [PC+2]
PC-register
← PC + 3 (point to next instruction)
CPU Cycles required:
3 cycles
Instruction:
Loads the next 2 bytes of program memory into CPU
register X. Register X can be any of the 16 CPU regis-
ters. Program counter (PC) is incremented twice during
the fetches of the next 2 bytes and incremented a third
time to point to the next instruction in program memory.
Two’s-complement data format is preserved.
No branching occurs.
No other registers are affected.
CLX Clear Register X
Op-code: 0001 XXXX
BINARY
1Xh
Operation:
X-register ← 0000h
PC-register
← PC + 1 (point to next instruction)
CPU Cycles required:
1 cycle
Description:
Clear the contents of register X to 0000h.
Register X can be any of the 16 CPU registers.
PC is incremented once to point to the next instruction
in program memory.
Two’s-complement data format is preserved.
No branching occurs.
No other registers are affected.
ANX AND Register X with Register A
Op-code: 0010 XXXX BINARY 2Xh
Operation:
A-register
← A-register AND X-register
PC-register ← PC + 1 (point to next instruction)
CPU Cycles required:
1 cycle
COMMAND OP CODE
(BITS 7–4)
REGISTER OP CODE
(BITS 3–0)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB LSB