Rainbow Electronics DS2188 - Manual (Page 2)

DS2188
021997 2/11
OVERVIEW
The RCLK input is fed to a 128 x 2–bit FIFO where it
drives the write pointer for the positive (RPOS) and neg-
ative (RNEG) data. The read pointer of the FIFO and
RRCLK is generated by dividing the frequency of the
crystal connected to XTAL1 and XTAL2 by four. The fre-
quency of the crystal is adjusted by a DPLL to the long–
term average frequency of RCLK. As long as the jitter
present at RCLK is less than 120 unit intervals peak–to–
peak (UIpp), then the FIFO buffer will be able to absorb
the incoming jitter and it will be attenuated in accor-
dance with TR 62411 (December 1990). In this situa-
tion, the BL (Buffer Limit) pin will remain low. Figures 1
and 2 illustrate the DS2188 Jitter Attenuator perfor-
mance.
If the incoming jitter has excursions greater than 120
UIpp, then the crystal is adjusted to track the short–term
frequency variations of the incoming signal so that there
is no loss of data. This adjustment is accomplished by
dividing the 4X crystal by either 3 1/2 or 4 1/2 instead of
4. When the incoming jitter is greater than 120UIpp, the
BL pin will transition high. When the incoming jitter re-
turns to less than 120UIpp, the BL pin will return low.
The jitter attenuator in the DS2188 can be disabled by
tying the DJA pin high. When the jitter attenuator is dis-
abled, the FIFO is bypassed and jitter received at RCLK,
RPOS and RNEG is passed through the DS2188 to
RRCLK, RRPOS, and RRNEG. In this situation, the BL
pin has no significance and XTAL OUT will not be co-
herent with RRCLK.
How to use the DS2188 with Dallas Semiconductor’s
other T1 and CEPT line interface parts is illustrated in
Figures 3 through 5. Figure 3 illustrates how to use the
DS2188 in the receive path along with a DS2187 Re-
ceive Line Interface. Figure 4 illustrates how to use the
DS2188 in the transmit path with the DS2186 Transmit
Line Interface. Also, see DS2188 Application Note,
“Operation at Speeds Greater than E1” for additional
information.
BUFFER DEPTH SELECT
The buffer size on the DS2188 can be configured to ei-
ther 128 or 32 bits via the BDS pin. If BDS is tied low,
then the buffer depth will be 128 bits and hence can han-
dle input jitter up to 120 UIpp without losing its full atten-
uation capabilities as is described above in the Over-
view. If BDS is tied high, then the buffer depth is
shortened to 32 bits. In this configuration, the DS2188
can handle input jitter up to 28 UIpp without losing its full
jitter attenuation capabilities. The user may wish to limit
the buffer size to 32 bits in applications where through-
put delay is critical or into existing applications that al-
ready have 32 bits of buffer space.
RESET
The buffer on the DS2188 is automatically centered on
power–up. The user can recenter the 128–bit (or 32–bit)
buffer on demand via the RST pin. The RST pin on the
DS2188 is negative–edge triggered. When this pin tran-
sitions from high–to–low, the buffer is recentered. The
RST pin can be held either high or low during operation
of the DS2188; only a negative going signal will initiate a
recentering. In most cases, a reset of the DS2188 will
corrupt data that is currently passing through the buffer.