Rainbow Electronics AT90S8515 - Manual (Page 61)

61
AT90S8515
0841G–09/01
Default, the external SRAM access, is a 3-cycle scheme as depicted in Figure 43. When
one extra wait state is needed in the access cycle, set the SRW bit (one) in the MCUCR
register. The resulting access scheme is shown in Figure 44. In both cases, note that
PORTA is data bus in one cycle only. As soon as the data access finishes, PORTA
becomes a low-order address bus again.
For details of the timing for the SRAM interface, please refer to Figure 68, Table 37,
Table 38, Table 39 and Table 40, beginning on page 92. Refer to “Architectural Over-
view” on page 7 for a description of the memory map, including address space for
SRAM.
Figure 42. External SRAM Connected to the AVR
Figure 43. External Data SRAM Memory Cycles without Wait State
D[7:0]
A[7:0]
A[15:8]
RD
WR
SRAM
D Q
G
Port A
ALE
Port C
RD
WR
AVR
System Clock Ø
ALE
WR
RD
Data/Address [7..0]
Data/Address [7..0]
Address [15..8]
Address
Address
Address
T1 T2 T3
Prev. Address
Prev. Address
Prev. Address
Data
Data
Wr
it
e
R
e
a
d
Address
Address