88 interrupt mask 1 register, 89 interrupt clear 0 register – Texas Instruments TVP5147M1PFP User Manual
Page 79
Functional Description
71
SLES140A—March 2007
TVP5147M1PFP
2.11.88 Interrupt Mask 1 Register
Subaddress
F5h
Default
00h
7
6
5
4
3
2
1
0
Reserved
H/V lock
Macrovision status changed
Standard changed
FIFO full
H/V lock: H/V lock status changed masked
0 = H/V lock status unchanged (default)
1 = H/V lock status changed
Macrovision status changed: Macrovision status changed mask
0 = Macrovision status unchanged
1 = Macrovision status changed
Standard changed: Standard changed mask
0 = Disabled (default)
1 = Enabled video standard changed
FIFO full: FIFO full mask
0 = Disabled (default)
1 = Enabled FIFO full interrupt
2.11.89 Interrupt Clear 0 Register
Subaddress
F6h
Default
00h
7
6
5
4
3
2
1
0
FIFO THRS
TTX
WSS
VPS
VITC
CC F2
CC F1
Line
FIFO THRS: FIFO threshold passed clear
0 = No effect (default)
1 = Clear bit 7 (FIFO_THRS) in the interrupt status 0 register at subaddress F2h
TTX: Teletext data available clear
0 = No effect (default)
1 = Clear bit 6 (TTX available) in the interrupt status 0 register at subaddress F2h
WSS: WSS data available clear
0 = No effect (default)
1 = Clear bit 5 (WSS available) in the interrupt status 0 register at subaddress F2h
VPS: VPS data available clear
0 = No effect (default)
1 = Clear bit 4 (VPS available) in the interrupt status 0 register at subaddress F2h
VITC: VITC data available clear
0 = Disabled (default)
1 = Clear bit 3 (VITC available) in the interrupt status 0 register at subaddress F2h
CC F2: CC field 2 data available clear
0 = Disabled (default)
1 = Clear bit 2 (CC field 2 available) in the interrupt status 0 register at subaddress F2h
CC F1: CC field 1 data available clear
0 = Disabled (default)
1 = Clear bit 1 (CC field 1 available) in the interrupt status 0 register at subaddress F2h