Texas Instruments TMS320F2802 - Manual (Page 73)

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015
www.ti.com SPRS230N – OCTOBER 2003 – REVISED MAY 2012
Enhanced features:
• Auto baud-detect hardware logic
• 16-level transmit/receive FIFO
The SCI port operation is configured and controlled by the registers listed in Table 4-8 and Table 4-9 .
Table 4-8. SCI-A Registers (1)
NAME ADDRESS SIZE (x16) DESCRIPTION
SCICCRA 0x7050 1 SCI-A Communications Control Register
SCICTL1A 0x7051 1 SCI-A Control Register 1
SCIHBAUDA 0x7052 1 SCI-A Baud Register, High Bits
SCILBAUDA 0x7053 1 SCI-A Baud Register, Low Bits
SCICTL2A 0x7054 1 SCI-A Control Register 2
SCIRXSTA 0x7055 1 SCI-A Receive Status Register
SCIRXEMUA 0x7056 1 SCI-A Receive Emulation Data Buffer Register
SCIRXBUFA 0x7057 1 SCI-A Receive Data Buffer Register
SCITXBUFA 0x7059 1 SCI-A Transmit Data Buffer Register
SCIFFTXA (2) 0x705A 1 SCI-A FIFO Transmit Register
SCIFFRXA (2) 0x705B 1 SCI-A FIFO Receive Register
SCIFFCTA (2) 0x705C 1 SCI-A FIFO Control Register
SCIPRIA 0x705F 1 SCI-A Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
(2) These registers are new registers for the FIFO mode.
Table 4-9. SCI-B Registers (1) (2)
NAME ADDRESS SIZE (x16) DESCRIPTION
SCICCRB 0x7750 1 SCI-B Communications Control Register
SCICTL1B 0x7751 1 SCI-B Control Register 1
SCIHBAUDB 0x7752 1 SCI-B Baud Register, High Bits
SCILBAUDB 0x7753 1 SCI-B Baud Register, Low Bits
SCICTL2B 0x7754 1 SCI-B Control Register 2
SCIRXSTB 0x7755 1 SCI-B Receive Status Register
SCIRXEMUB 0x7756 1 SCI-B Receive Emulation Data Buffer Register
SCIRXBUFB 0x7757 1 SCI-B Receive Data Buffer Register
SCITXBUFB 0x7759 1 SCI-B Transmit Data Buffer Register
SCIFFTXB (2) 0x775A 1 SCI-B FIFO Transmit Register
SCIFFRXB (2) 0x775B 1 SCI-B FIFO Receive Register
SCIFFCTB (2) 0x775C 1 SCI-B FIFO Control Register
SCIPRIB 0x775F 1 SCI-B Priority Control Register
(1) Registers in this table are mapped to peripheral bus 16 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
(2) These registers are new registers for the FIFO mode.
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