Section 5.16 – Texas Instruments TMS320DM36X User Manual
Page 98
Ethernet Media Access Controller (EMAC) Registers
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5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)
The receive interrupt mask clear register (RXINTMASKCLEAR) is shown in
and described in
.
Figure 55. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)
31
16
Reserved
R-0
15
8
Reserved
R-0
7
6
5
4
3
2
1
0
RX7MASK
RX6MASK
RX5MASK
RX4MASK
RX3MASK
RX2MASK
RX1MASK
RX0MASK
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
R/W1C-0
LEGEND: R = Read only; R/W = Read/Write; W1C = Write 1 to clear, write of 0 has no effect; -n = value after reset
Table 53. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reserved
7
RX7MASK
0-1
Receive channel 7 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
6
RX6MASK
0-1
Receive channel 6 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
5
RX5MASK
0-1
Receive channel 5 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
4
RX4MASK
0-1
Receive channel 4 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
3
RX3MASK
0-1
Receive channel 3 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
2
RX2MASK
0-1
Receive channel 2 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
1
RX1MASK
0-1
Receive channel 1 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
0
RX0MASK
0-1
Receive channel 0 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
98
Ethernet Media Access Controller (EMAC)/Management Data Input/Output
SPRUFI5B – March 2009 – Revised December 2010
(MDIO)
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