Section 5.46, Section 5.47 – Texas Instruments TMS320DM36X User Manual
Page 121
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Ethernet Media Access Controller (EMAC) Registers
5.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TXnHDP)
The transmit channel 0-7 DMA head descriptor pointer register (TXnHDP) is shown in
and
described in
.
Figure 85. Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP)
31
16
TXnHDP
R/W-x
15
0
TXnHDP
R/W-x
LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset
Table 83. Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP)
Field Descriptions
Bit
Field
Value
Description
31-0
TXnHDP
0-FFFF FFFFh
Transmit channel n DMA Head Descriptor pointer. Writing a transmit DMA buffer descriptor
address to a head pointer location initiates transmit DMA operations in the queue for the
selected channel. Writing to these locations when they are nonzero is an error (except at reset).
Host software must initialize these locations to 0 on reset.
5.47 Receive Channel 0-7 DMA Head Descriptor Pointer Register (RXnHDP)
The receive channel 0-7 DMA head descriptor pointer register (RXnHDP) is shown in
and
described in
.
Figure 86. Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP)
31
16
RXnHDP
R/W-x
15
0
RXnHDP
R/W-x
LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset
Table 84. Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP)
Field Descriptions
Bit
Field
Value
Description
31-0
RXnHDP
0-FFFF FFFFh
Receive channel n DMA Head Descriptor pointer. Writing a receive DMA buffer descriptor
address to this location allows receive DMA operations in the selected channel when a channel
frame is received. Writing to these locations when they are nonzero is an error (except at reset).
Host software must initialize these locations to 0 on reset.
121
SPRUFI5B – March 2009 – Revised December 2010
Ethernet Media Access Controller (EMAC)/Management Data Input/Output
(MDIO)
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