4 industry standard(s) compliance statement, 2 architecture, 1 clock control – Texas Instruments TMS320DM36X User Manual
Page 15: 1 mii clocking
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Architecture
The EMAC and MDIO interrupts are combined within the control module, so only the control module
interrupt needs to be monitored by the application software or device driver. The EMAC control module
combines the EMAC and MDIO interrupts and generates 4 separate interrupts to the ARM through the
ARM interrupt controller. See
for details of interrupt multiplex logic of the EMAC control
module.
1.4
Industry Standard(s) Compliance Statement
The EMAC peripheral conforms to the IEEE 802.3 standard, describing the Carrier Sense Multiple Access
with Collision Detection (CSMA/CD) Access Method and Physical Layer specifications. The IEEE 802.3
standard has also been adopted by ISO/IEC and re-designated as ISO/IEC 8802-3:2000(E).
In difference from this standard, the EMAC peripheral does not use the Transmit Coding Error signal
MTXER. Instead of driving the error pin when an underflow condition occurs on a transmitted frame, the
EMAC intentionally generates an incorrect checksum by inverting the frame CRC, so that the transmitted
frame is detected as an error by the network.
2
Architecture
This section discusses the architecture and basic function of the EMAC/MDIO module.
2.1
Clock Control
The frequencies for the transmit and receive clocks are fixed by the IEEE 802.3 specification as:
•
2.5 MHz at 10 Mbps
•
25 MHz at 100 Mbps
All EMAC logic is clocked synchronously with the PLL peripheral clock. The MDIO clock can be controlled
through the application software, by programming the divide-down factor in the MDIO control register
(CONTROL).
2.1.1
MII Clocking
The transmit and receive clock sources are provided from an external PHY via the EMAC_TX_CLK and
EMAC_RX_CLK pins. These clocks are inputs to the EMAC module and operate at 2.5 MHz in 10 Mbps
mode and at 25 MHz in 100 Mbps mode. For timing purposes, data is transmitted and received with
reference to EMAC_TX_CLK and EMAC_RX_CLK, respectively.
15
SPRUFI5B – March 2009 – Revised December 2010
Ethernet Media Access Controller (EMAC)/Management Data Input/Output
(MDIO)
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