3 transmit and receive emac interrupts – Texas Instruments TMS320DM36X User Manual
Page 22
Architecture
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2.6.3
Transmit and Receive EMAC Interrupts
The EMAC processes descriptors in linked list chains as discussed in
, using the linked list
queue mechanism discussed in
.
The EMAC synchronizes descriptor list processing through the use of interrupts to the software
application. The interrupts are controlled by the application using the interrupt masks, global interrupt
enable, and the completion pointer register (CP). The CP is also called the interrupt acknowledge register.
As the EMAC supports eight channels for both transmit and receive, there are eight completion pointer
registers for both. They are:
•
TXnCP - Transmit Channel n Completion Pointer (Interrupt Acknowledge) Register
•
RXnCP - Receive Channel n Completion Pointer (Interrupt Acknowledge) Register
These registers serve two purposes. When read, they return the pointer to the last descriptor that the
EMAC has processed. When written by the software application, the value represents the last descriptor
processed by the software application. When these two values do not match, the interrupt remains
asserted, after the respective End of interrupt bit is signaled in the EMAC control module.
The system configuration determines whether or not an active interrupt actually interrupts the CPU. In
general, the individual interrupts for different events from the EMAC and MDIO must be enabled in the
EMAC control module, and it also must be mapped in the ARM interrupt controller and enabled as a CPU
interrupt. If the system is configured properly, the interrupt for a specific receive or transmit channel
executes under the previously described conditions when the corresponding interrupt is enabled in the
EMAC using the receive interrupt mask set register (RXINTMASKSET) or the transmit interrupt mask set
register (TXINTMASKSET).
Whether or not the interrupt is enabled, the current state of the receive or transmit channel interrupt can
be examined directly by the software application reading the receive interrupt status (unmasked) register
(RXINTSTATRAW) and transmit interrupt status (unmasked) register (TXINTSTATRAW).
Interrupts are acknowledged when the application software updates the value of TXnCP or RXnCP with a
value that matches the internal value kept by the EMAC. This mechanism ensures that the application
software never misses an EMAC interrupt, since the interrupt and its acknowledgment are tied directly to
the actual buffer descriptors processing.
22
Ethernet Media Access Controller (EMAC)/Management Data Input/Output
SPRUFI5B – March 2009 – Revised December 2010
(MDIO)
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