Texas Instruments TMS320DM36X - Manual (Page 38)

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2.9.1.3 MAC Receiver
The MAC receiver detects and processes incoming network frames, de-frames them, and puts them into
the receive FIFO. The MAC receiver also detects errors and passes statistics to the statistics RAM.
2.9.1.4 Receive Address
This sub-module performs address matching and address filtering based on the incoming packet’s
destination address. It contains a 32-by-53 bit two-port RAM, in which up to 32 addresses can be stored to
be either matched or filtered by the EMAC. The RAM may contain multicast packet addresses, but the
associated channel must have the unicast enable bit set, even though it is a multicast address. The
unicast enable bits are used with multicast addresses in the receive address RAM (not the multicast hash
enable bits). Therefore, hash matches can be disabled, but specific multicast addresses can be matched
(or filtered) in the RAM. If a multicast packet hash matches, the packet may still be filtered in the RAM.
Each packet can be sent to only a single channel.
2.9.1.5 Transmit DMA Engine
The transmit DMA engine is the interface between the transmit FIFO and the CPU. It interfaces to the
CPU through the bus arbiter in the EMAC control module.
2.9.1.6 Transmit FIFO
The transmit FIFO consists of 24 cells of 64 bytes each and associated control logic. This enables a
packet of 1518 bytes (standard Ethernet packet size) to be sent without the possibility of underrun. The
FIFO buffers data in preparation for transmission.
2.9.1.7 MAC Transmitter
The MAC transmitter formats frame data from the transmit FIFO and transmits the data using the
CSMA/CD access protocol. The frame CRC can be automatically appended, if required. The MAC
transmitter also detects transmission errors and passes statistics to the statistics registers.
2.9.1.8 Statistics Logic
The Ethernet statistics are counted and stored in the statistics logic RAM. This statistics RAM keeps track
of 36 different Ethernet packet statistics.
2.9.1.9 State RAM
State RAM contains the head descriptor pointers and completion pointers registers for both transmit and
receive channels.
2.9.1.10 EMAC Interrupt Controller
The interrupt controller contains the interrupt related registers and logic. The 18 raw EMAC interrupts are
input to this submodule and masked module interrupts are output.
2.9.1.11 Control Registers and Logic
The EMAC is controlled by a set of memory-mapped registers. The control logic also signals transmit,
receive, and status related interrupts to the CPU through the EMAC control module.
2.9.1.12 Clock and Reset Logic
The clock and reset submodule generates all the EMAC clocks and resets. For more details on reset
capabilities, see
Section 2.15.1 .
38 Ethernet Media Access Controller (EMAC)/Management Data Input/Output SPRUFI5B – March 2009 – Revised December 2010
(MDIO)
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