Rockwell SoniCrafter BT8960 - Manual (Page 74)

64
3.0 Registers
3.1 Conventions
Bt8960
Single-Chip 2B1Q Transceiver
N8960DSB
3.2.46 0x40, 0x41—Phase Detector Meter Register (pdm_low, pdm_high)
A 2-byte read-only register containing the 16 MSBs of the 26-bit, 2’s-complement phase detector meter accu-
mulator. This meter sums the output of the timing recovery module’s phase detector—prior to being offset by
the Phase Offset Register [pll_phase_offset_low, pll_phase_offset_high; 0x24, 0x25]—over each Meter Timer
countdown interval. Automatically loaded at the end of each interval, the meter register must be read low byte
first, followed by high byte, unseparated by any other meter-register read access.
3.2.47 0x42—Overflow Meter Register (overflow_meter)
A single-byte read-only register containing all 8 bits of the unsigned overflow meter accumulator. This meter
counts the number of ADC overflow conditions which occur during each Meter Timer countdown interval, lim-
ited to a maximum count of 255 (0xFF). The meter register is automatically loaded at the end of each count-
down interval.
3.2.48 0x44, 0x45—DC Level Meter Register (dc_meter_low, dc_meter_high)
A 2-byte read-only register containing the 16 MSBs of the 32-bit, 2’s-complement DC-level meter accumulator.
This meter sums the value of the receive signal input path—after format conversion and DC offset correction
but before echo cancellation—over each Meter Timer countdown interval. Automatically loaded at the end of
each interval, the meter register must be read low byte first, followed by high byte, unseparated by any other
meter-register read access.
7 6 5 4 3 2 1 0
D[17] D[16] D[15] D[14] D[13] D[12] D[11] D[10]
D[25] D[24] D[23] D[22] D[21] D[20] D[19] D[18]
7 6 5 4 3 2 1 0
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
7 6 5 4 3 2 1 0
D[23] D[22] D[21] D[20] D[19] D[18] D[17] D[16]
D[31] D[30] D[29] D[28] D[27] D[26] D[25] D[24]