Rockwell SoniCrafter BT8960 - Manual (Page 13)

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1.0 System Overview
1.1 Functional Summary
Bt8960
Single-Chip 2B1Q Transceiver
N8960DSB
1.1.1 Transmit Section
The source of transmitted symbols is programmable through the microcomputer
interface. The primary choices include external 2B1Q-encoded data presented to
the TQ[1,0]/TDAT pins of the channel unit interface, internally looped-back
receive symbols from the detector, or a constant “all ones” source. The symbols
are then optionally scrambled. Isolated pulses can also be generated to support
the testing of pulse templates.
The digital symbols are transformed to an analog signal via the DAC, which is
highly linear in order to maximize the echo cancellation and detection properties
of the signal. In addition, the transmit power level of the DAC may be adjusted
via the Transmitter Gain Register [tx_gain; 0x29] to optimize performance. The
Transmitter Calibration Register [tx_calibrate; 0x28] contains the nominal setting
for the transmitter gain which is calibrated and hard-coded at the factory. The
pulse-shaping filter then conditions the signal to prevent crosstalk to adjacent sub-
scriber lines. Finally, the differential line driver provides the current driving capa-
bilities and low-distortion characteristics needed to drive a large range of
subscriber lines at low-bit error rates.
1.1.2 Receive Section
The differential Variable Gain Amplifier (VGA) receives the data from the sub-
scriber line. Balancing inputs (RXBP, RXBN) are provided to accommodate first-
order transmit echo cancellation via an external hybrid. The gain is programma-
ble so that the dynamic range of the Analog-to-Digital Converter (ADC) can be
maximized according to the attenuation of the subscriber line.
Digitized receive data is passed to the Digital Signal Processor (DSP) portion
of the Bt8960. After DC offset cancellation, a replica of the transmit signal is sub-
tracted from the total receive signal by a digital echo canceler. The resultant far-
end signal is then conditioned by an equalization stage consisting of Automatic
Gain Control (AGC), a feed-forward equalizer, a decision-feedback equalizer,
and an error predictor. A mode-dependent detector is then used to recover the
2B1Q-encoded data from the equalized signal. The channel unit interface then
provides an optional descrambling function followed by parallel or serial output
of the sign and magnitude bits on pins RQ[1,0]/RDAT. A number of meters are
implemented within the receiver to provide average level indications at various
points in the receive signal path. The receive section also performs remote unit
clock recovery through an on-chip Phase Lock Loop (PLL) circuit.
1.1.3 Timing Recovery and Clock Interface
The clock interface includes a crystal amplifier module to reduce the external
components needed for clock generation. The crystal frequency must be 64 times
the desired symbol rate. When configured as a remote unit, the PLL module
recovers the incoming data clock and outputs it on the QCLK pin (and also the
BCLK pin for serial mode operation). The HCLK output, which is synchronized
to the QCLK signal, can be configured to cycle at 16, 32, or 64 times the symbol
rate.