Rockwell SoniCrafter BT8960 - Manual (Page 43)

33
2.0 Functional Description
2.5 Microcomputer Interface
Bt8960
Single-Chip 2B1Q Transceiver
N8960DSB
2.5.2.1 RAM Access
Registers
The internal RAMs of the transmit filter, LEC, NEC, DFE, equalizer, and micro-
code are accessed indirectly. They all share a common data register which is used
for both read and write operations: Access Data Register [access_data_byte[3:0];
[0x7C–0x7F]. Each RAM has an individual read select and write select register.
These registers specify the location to access and trigger the actual RAM read or
write.
To perform a read, the address of the desired RAM location is first written to
the corresponding read tap select register. Two symbol periods afterwards, the
individual bytes of that location are available for reading from the Access Data
Register.
To perform a write, the value to be written is first stored in the Access Data
Register. The address of the affected RAM location is then written to the corre-
sponding write tap select register. When writing the same value to multiple loca-
tions, it is not necessary to rewrite the Access Data Register.
To assure reliable access to the embedded RAMs, internal read and write
operations are performed synchronous to the symbol clock. This has the effect of
limiting access to these internal RAMs to one every other cycle.
When reading or writing multiple filter coefficients, it may be desirable to
freeze adaptation so that all values will correspond to the same state.
2.5.2.2 Multiplexed
Address/Data Bus
The timing for a read or write cycle is stated explicitly in the Electrical and
Mechanical Specifications section. During a read operation, an external micro-
computer places an address on the address-data bus which is then latched on the
falling edge of ALE. Data is placed on the address-data bus after CS, RD, or DS
go low. The read cycle is completed with the rising edge of CS, RD, or DS.
A write operation latches the address from the address-data bus at the falling
edge of ALE. The microcomputer places data on the address-data bus after CS,
WR, or DS go low. Motorola MCI will have R/W falling edge preceding the fall-
ing edge of CS and DS. The rising edge of R/W will occur after the rising edge of
CS and DS. Data is latched on the address-data bus on the rising edge of WR or
DS.
2.5.2.3 Separated
Address/
Data Bus
The timing for a read or write cycle using the separated address and data buses is
essentially the same as over the multiplexed bus. The one exception is that the
address must be driven onto the ADDR[7:0] bus rather than the AD[7:0] bus.
2.5.3 Interrupt Request
The twelve interrupt sources consist of: eight timers, a far-end signal high alarm,
a far-end signal low alarm, a SNR alarm, and a scrambler synchronization detec-
tion. All of the interrupts are requested on a common pin, IRQ. Each interrupt
may be individually enabled or disabled through the Interrupt Mask Registers
[mask_low_reg, mask_high_reg; 0x02, 0x03]. The cause of an interrupt is deter-
mined by reading the Timer Source Register [timer_source; 0x04] and the IRQ
Source Register [irq_source; 0x05].
The timer interrupt status is set only when the timer transitions to zero. Alarm
interrupts cannot be cleared while the alarm is active. In other words, it cannot be
cleared while the condition still exists.
IRQ is an open-drain output and must be tied to a pull-up resistor. This allows
IRQ to be tied together with a common interrupt request.