Silicon Laboratories C8051F347 - Manual (Page 85)

Rev. 1.3 85
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
SBUF0 0x99 UART0 Data Buffer 211
SCON0 0x98 UART0 Control 210
SMB0CF 0xC1 SMBus Configuration 194
SMB0CN 0xC0 SMBus Control 196
SMB0DAT 0xC2 SMBus Data 198
SMOD1 0xE5 UART1 Mode 219
SP 0x81 Stack Pointer 86
SPI0CFG 0xA1 SPI Configuration 229
SPI0CKR 0xA2 SPI Clock Rate Control 231
SPI0CN 0xF8 SPI Control 230
SPI0DAT 0xA3 SPI Data 231
TCON 0x88 Timer/Counter Control 239
TH0 0x8C Timer/Counter 0 High 242
TH1 0x8D Timer/Counter 1 High 242
TL0 0x8A Timer/Counter 0 Low 242
TL1 0x8B Timer/Counter 1 Low 242
TMOD 0x89 Timer/Counter Mode 240
TMR2CN 0xC8 Timer/Counter 2 Control 247
TMR2H 0xCD Timer/Counter 2 High 248
TMR2L 0xCC Timer/Counter 2 Low 248
TMR2RLH 0xCB Timer/Counter 2 Reload High 248
TMR2RLL 0xCA Timer/Counter 2 Reload Low 248
TMR3CN 0x91 Timer/Counter 3Control 253
TMR3H 0x95 Timer/Counter 3 High 254
TMR3L 0x94 Timer/Counter 3Low 254
TMR3RLH 0x93 Timer/Counter 3 Reload High 254
TMR3RLL 0x92 Timer/Counter 3 Reload Low 254
VDM0CN 0xFF V
DD
Monitor Control 102
USB0ADR 0x96 USB0 Indirect Address Register 163
USB0DAT 0x97 USB0 Data Register 164
USB0XCN 0xD7 USB0 Transceiver Control 161
XBR0 0xE1 Port I/O Crossbar Control 0 148
XBR1 0xE2 Port I/O Crossbar Control 1 149
XBR2 0xE3 Port I/O Crossbar Control 2 149
All Other Addresses Reserved
Table 9.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
Register
Address Description Page