Silicon Laboratories C8051F344 Instruction Manuals and User Guides

We have 1 Instruction Manual and User Guide for C8051F344 Silicon Laboratories

Silicon Laboratories C8051F344 User Manual, 276 pages

Recognized languages:	English
Pages:	276
Size:	1.78 MB

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Document Outline

Table of Contents
List of Figures
List of Tables
List of Registers
1. System Overview
- Table 1.1. Product Selection Guide
- Figure 1.1. C8051F340/1/4/5 Block Diagram
- Figure 1.2. C8051F342/3/6/7 Block Diagram
- Figure 1.3. C8051F348/C Block Diagram
- Figure 1.4. C8051F349/D Block Diagram
- Figure 1.5. C8051F34A/B Block Diagram
2. Absolute Maximum Ratings
- Table 2.1. Absolute Maximum Ratings*
3. Global DC Electrical Characteristics
- Table 3.1. Global DC Electrical Characteristics
- Table 3.2. Index to Electrical Characteristics Tables
4. Pinout and Package Definitions
- Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
- Figure 4.1. TQFP-48 Pinout Diagram (Top View)
- Figure 4.2. TQFP-48 Package Diagram
- Table 4.2. TQFP-48 Package Dimensions
- Figure 4.3. TQFP-48 Recommended PCB Land Pattern
- Table 4.3. TQFP-48 PCB Land Pattern Dimensions
- Figure 4.4. LQFP-32 Pinout Diagram (Top View)
- Figure 4.5. LQFP-32 Package Diagram
- Table 4.4. LQFP-32 Package Dimensions
- Figure 4.6. LQFP-32 Recommended PCB Land Pattern
- Table 4.5. LQFP-32 PCB Land Pattern Dimensions
- Figure 4.7. QFN-32 Pinout Diagram (Top View)
5. 10-Bit ADC (ADC0, C8051F340/1/2/3/4/5/6/7/A/B Only)
- Figure 5.1. ADC0 Functional Block Diagram
- 5.1. Analog Multiplexer
- 5.2. Temperature Sensor
  - Figure 5.2. Temperature Sensor Transfer Function
  - Figure 5.3. Temperature Sensor Error with 1-Point Calibration (VREF = 2.40 V)
- 5.3. Modes of Operation
- 5.4. Programmable Window Detector
6. Voltage Reference (C8051F340/1/2/3/4/5/6/7/A/B Only)
- Figure 6.1. Voltage Reference Functional Block Diagram
- SFR Definition 6.1. REF0CN: Reference Control
- Table 6.1. Voltage Reference Electrical Characteristics
7. Comparators
- Figure 7.1. Comparator Functional Block Diagram
- Figure 7.2. Comparator Hysteresis Plot
- SFR Definition 7.1. CPT0CN: Comparator0 Control
- SFR Definition 7.2. CPT0MX: Comparator0 MUX Selection
- SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection
- SFR Definition 7.4. CPT1CN: Comparator1 Control
- SFR Definition 7.5. CPT1MX: Comparator1 MUX Selection
- SFR Definition 7.6. CPT1MD: Comparator1 Mode Selection
- Table 7.1. Comparator Electrical Characteristics
8. Voltage Regulator (REG0)
- 8.1. Regulator Mode Selection
- 8.2. VBUS Detection
9. CIP-51 Microcontroller
- Figure 9.1. CIP-51 Block Diagram
- 9.1. Instruction Set
- 9.2. Memory Organization
- 9.3. Interrupt Handler
- 9.4. Power Management Modes
10. Prefetch Engine
- SFR Definition 10.1. PFE0CN: Prefetch Engine Control
11. Reset Sources
- Figure 11.1. Reset Sources
- 11.1. Power-On Reset
  - Figure 11.2. Power-On and VDD Monitor Reset Timing
- 11.2. Power-Fail Reset / VDD Monitor
  - SFR Definition 11.1. VDM0CN: VDD Monitor Control
- 11.3. External Reset
- 11.4. Missing Clock Detector Reset
- 11.5. Comparator0 Reset
- 11.6. PCA Watchdog Timer Reset
- 11.7. Flash Error Reset
- 11.8. Software Reset
- 11.9. USB Reset
  - SFR Definition 11.2. RSTSRC: Reset Source
  - Table 11.1. Reset Electrical Characteristics
12. Flash Memory
- 12.1. Programming The Flash Memory
- 12.2. Non-Volatile Data Storage
- 12.3. Security Options
13. External Data Memory Interface and On-Chip XRAM
- 13.1. Accessing XRAM
  - 13.1.1. 16-Bit MOVX Example
  - 13.1.2. 8-Bit MOVX Example
- 13.2. Accessing USB FIFO Space
  - Figure 13.1. USB FIFO Space and XRAM Memory Map with USBFAE set to ‘1’
- 13.3. Configuring the External Memory Interface
- 13.4. Port Configuration
  - SFR Definition 13.1. EMI0CN: External Memory Interface Control
  - SFR Definition 13.2. EMI0CF: External Memory Configuration
- 13.5. Multiplexed and Non-multiplexed Selection
- 13.6. Memory Mode Selection
- 13.7. Timing
14. Oscillators
- Figure 14.1. Oscillator Diagram
- 14.1. Programmable Internal High-Frequency (H-F) Oscillator
- 14.2. Programmable Internal Low-Frequency (L-F) Oscillator
  - 14.2.1. Calibrating the Internal L-F Oscillator
  - SFR Definition 14.3. OSCLCN: Internal L-F Oscillator Control
- 14.3. External Oscillator Drive Circuit
- 14.4. 4x Clock Multiplier
  - SFR Definition 14.5. CLKMUL: Clock Multiplier Control
- 14.5. System and USB Clock Selection
15. Port Input/Output
- Figure 15.1. Port I/O Functional Block Diagram (Port 0 through Port 3)
- Figure 15.2. Port I/O Cell Block Diagram
- 15.1. Priority Crossbar Decoder
- 15.2. Port I/O Initialization
- 15.3. General Purpose Port I/O
16. Universal Serial Bus Controller (USB0)
- Figure 16.1. USB0 Block Diagram
- 16.1. Endpoint Addressing
  - Table 16.1. Endpoint Addressing Scheme
- 16.2. USB Transceiver
  - SFR Definition 16.1. USB0XCN: USB0 Transceiver Control
- 16.3. USB Register Access
- 16.4. USB Clock Configuration
  - USB Register Definition 16.5. CLKREC: Clock Recovery Control
- 16.5. FIFO Management
- 16.6. Function Addressing
  - USB Register Definition 16.7. FADDR: USB0 Function Address
- 16.7. Function Configuration and Control
- 16.8. Interrupts
- 16.9. The Serial Interface Engine
- 16.10. Endpoint0
- 16.11. Configuring Endpoints1-3
- 16.12. Controlling Endpoints1-3 IN
- 16.13. Controlling Endpoints1-3 OUT
17. SMBus
- Figure 17.1. SMBus Block Diagram
- 17.1. Supporting Documents
- 17.2. SMBus Configuration
  - Figure 17.2. Typical SMBus Configuration
- 17.3. SMBus Operation
- 17.4. Using the SMBus
- 17.5. SMBus Transfer Modes
- 17.6. SMBus Status Decoding
  - Table 17.4. SMBus Status Decoding
18. UART0
- Figure 18.1. UART0 Block Diagram
- 18.1. Enhanced Baud Rate Generation
  - Figure 18.2. UART0 Baud Rate Logic
- 18.2. Operational Modes
- 18.3. Multiprocessor Communications
19. UART1 (C8051F340/1/4/5/8/A/B/C Only)
- Figure 19.1. UART1 Block Diagram
- 19.1. Baud Rate Generator
  - Table 19.1. Baud Rate Generator Settings for Standard Baud Rates
- 19.2. Data Format
- 19.3. Configuration and Operation
20. Enhanced Serial Peripheral Interface (SPI0)
- Figure 20.1. SPI Block Diagram
- 20.1. Signal Descriptions
- 20.2. SPI0 Master Mode Operation
- 20.3. SPI0 Slave Mode Operation
- 20.4. SPI0 Interrupt Sources
- 20.5. Serial Clock Timing
- 20.6. SPI Special Function Registers
21. Timers
- 21.1. Timer 0 and Timer 1
- 21.2. Timer 2
- 21.3. Timer 3
22. Programmable Counter Array (PCA0)
- Figure 22.1. PCA Block Diagram
- 22.1. PCA Counter/Timer
  - Table 22.1. PCA Timebase Input Options
  - Figure 22.2. PCA Counter/Timer Block Diagram
- 22.2. Capture/Compare Modules
- 22.3. Watchdog Timer Mode
- 22.4. Register Descriptions for PCA
23. C2 Interface
- 23.1. C2 Interface Registers
- 23.2. C2 Pin Sharing
  - Figure 23.1. Typical C2 Pin Sharing
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