Silicon Laboratories C8051F347 - Manual (Page 80)

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
80 Rev. 1.3
Figure 9.3. On-Chip Memory Map for 32 kB Devices
9.2.1. Program Memory
The CIP-51 core has a 64k-byte program memory space. The C8051F34x implements 64k or 32k bytes of
this program memory space as in-system, re-programmable Flash memory. Note that on the 64k versions
of the C8051F34x, addresses above 0xFBFF are reserved.
Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory
by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature pro-
vides a mechanism for the CIP-51 to update program code and use the program memory space for
non-volatile data storage. Refer to
Section “12. Flash Memory” on page 107 for further details.
PROGRAM/DATA MEMORY
(FLASH)
(Direct and Indirect
Addressing)
0x00
0x7F
Upper 128 RAM
(Indirect Addressing
Only)
0x80
0xFF
Special Function
Register's
(Direct Addressing Only)
DATA MEMORY (RAM)
General Purpose
Registers
0x1F
0x20
0x2F
Bit Addressable
Lower 128 RAM
(Direct and Indirect
Addressing)
0x30
INTERNAL DATA ADDRESS SPACE
EXTERNAL DATA ADDRESS SPACE
XRAM - 2048 Bytes
(Accessable using MOVX
instruction)
0x0000
0x07FF
Off-Chip XRAM
(Available only on devices
with EMIF)
0x0400
0xFFFF
FLASH
(In-System
Programmable in 512
Byte Sectors)
0x0000
0x7FFF
USB FIFOs
1024 Bytes
0x07FF
0x0800