Silicon Laboratories C8051F347 - Manual (Page 12)

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
12 Rev. 1.3
Table 17.2. Minimum SDA Setup and Hold Times ................................................ 193
Table 17.3. Sources for Hardware Changes to SMB0CN ..................................... 197
Table 17.4. SMBus Status Decoding ..................................................................... 203
18. UART0
Table 18.1. Timer Settings for Standard Baud Rates

Using the Internal Oscillator ............................................................... 212
19. UART1 (C8051F340/1/4/5/8/A/B/C Only)
Table 19.1. Baud Rate Generator Settings for Standard Baud Rates ................... 214
20. Enhanced Serial Peripheral Interface (SPI0)
Table 20.1. SPI Slave Timing Parameters ............................................................ 234
22. Programmable Counter Array (PCA0)
Table 22.1. PCA Timebase Input Options ............................................................. 256
Table 22.2. PCA0CPM Register Settings for PCA Capture/Compare Modules .... 257
Table 22.3. Watchdog Timer Timeout Intervals1 ................................................... 265