Intel 8XC196Lx - Manual (Page 68)

8XC196L X SUPPLEMENT
8-2
The J1850 controller can handle network protocol functions including message frame sequenc-
ing, bit arbitration, in-frame response (IFR) messaging, error detection, and delay compensation.
The J1850 communications controller (Figure 8-2) consists of a control state machine (CSM),
symbol synchronization and timing (SST) circuitry, six control and status registers, transmit and
receive buffers, and an interrupt handler.
Figure 8-2. J1850 Communications Controller Block Diagram
A5169-01
Peripheral Data Bus
J_CFG
J_CMD
J_RX
JRX_BUF
JTX_BUF
J_TX
J_STAT
J_DLY
Interrupt
Handler
J1850ST
J1850RX
J1850TX
OVR
UNDR
TX
RX
Bus Error
Error
Detection
Circuitry
Bit
Arbitration
Circuitry
Cyclic
Redundancy
Check Circuitry
CSM
Symbol
Encoder
Symbol
Decoder
Prescaler
Delay
Compensator
SST
Digital
Filter
Internal Clocking
TXJ1850
RXJ1850
J1850 Communications Controller