Intel 8XC196Lx - Manual (Page 96)

8XC196L X SUPPLEMENT
10-2
Figure 10-1. Clock Circuitry (87C196LA, LB Only)
10.2 ENTERING AND EXITING ONCE MODE
ONCE mode isolates the device from other components in the system to allow printed-circuit-
board testing or debugging with a clip-on emulator. During ONCE mode, all pins except XTAL1,
XTAL2, V
SS
, and V
CC
are weakly pulled either high or low. During ONCE mode, RESET# must
be held high or the device will exit ONCE mode and enter the reset state.
On the 87C196LA and LB, the reset state level of all 41 general-purpose I/O pins has changed
from a weak logic “1” (wk1) to a weak logic “0” (wk0). ONCE shares a package with port pin
2.6. Asserting and holding the ONCE signal high during the rising edge of RESET# causes the
device to enter ONCE mode. To prevent accidental entry into ONCE mode, configure this pin as
Phase-locked Loop
Clock Multiplier
Phase
Comparator
Filter
Phase-locked
Oscillator
A5290-01
Disable
PLL
(Powerdown)
XTAL1
XTAL2
F
XTAL1
Disable Oscillator
(Powerdown)
0
1
Disable Clocks (Idle, Powerdown)
1
0
PLLEN
2F
XTAL1
Clock
Generators
Programmable
Divider
(CLK1:0)
Disable Clock Input (Powerdown)
CPU Clocks (PH1, PH2)
Peripheral Clocks (PH1, PH2)
Disable Clocks (Powerdown)
CLKOUT
f
f/2
OSC
F
XTAL1
f/2
Divide by two
Circuit
Clock
Failure
Detection
To reset logic