Intel 8XC196Lx - Manual (Page 62)

8XC196L X SUPPLEMENT
7-4
7.1.1 EPA Mask Registers
Figures 7-3 and 7-4 illustrate the EPA mask registers, EPA_MASK and EPA_MASK1, for the
8XC196Lx microcontroller family.
EPA_MASK Address:
Reset State:
1FA0H
0000H
The EPA interrupt mask (EPA_MASK) register enables or disables (masks) interrupts associated with
the shared EPA
x interrupt.
15 8
Lx — — EPA6 EPA7 EPA8 EPA9 OVR0 OVR1
7 0
0VR2 OVR3 — — — — OVR8 OVR9
Bit
Number
Function
15:0 † Setting a bit enables the corresponding interrupt as a EPA x interrupt source. The shared
EPA x interrupt is enabled by setting its interrupt enable bit in the interrupt mask register
(INT_MASK.0 = 1).
† Bits 2–5 and 14–15 are reserved on the 8XC196L x device family. For compatibility with future
devices, write zeros to these bits.
Figure 7-3. EPA Interrupt Mask (EPA_MASK) Register
EPA_MASK1 Address:
Reset State:
1FA4H
00H
The EPA interrupt mask 1 (EPA_MASK1) register enables or disables (masks) interrupts associated
with the multiplexed EPA
x interrupt.
7 0
— — — — COMP0 † COMP1 † OVRTM1 OVRTM2
Bit
Number
Function
7:4 Reserved; for compatibility with future devices, write zeros to these bits.
3:0 † Setting a bit enables the corresponding interrupt as a multiplexed EPA x interrupt source.
The multiplexed EPA x interrupt is enabled by setting its interrupt enable bit in the
interrupt mask register (INT_MASK.0 = 1).
† 87C196LA, LB only; reserved on 83C196LD.
Figure 7-4. EPA Interrupt Mask 1 (EPA_MASK1) Register