Figure 52. ports 3 and 4 internal structure (87c1, 8xc196l x supplement – Intel 8XC196Lx User Manual
Page 50
8XC196L
X SUPPLEMENT
5-6
Figure 5-2. Ports 3 and 4 Internal Structure (87C196LA, LB Only)
Q2
Q1
P
x
_REG
P34_DRV
Sample
Latch
PH1 Clock
Internal Bus
Address/Data
P
x
_PIN
D
Q
Weak
Pullup
RESET#
Q3
Q4
Buffer
Read Port
LE
300ns Delay
I/O Pin
Bus Control Select
0 = Address/Data
1 = I/O
RESET#
A5264-01
150
Ω
to 200
Ω
R1
1
0
V
SS
Medium
Pullup
V
SS
V
SS
V
CC
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