Intel 8XC196Lx - Manual (Page 135)

Index-1
INDEX
A
Address map, 3-1
Address partitions
map, 3-1
OTPROM, 11-1
program memory, 11-1
special-purpose memory, 11-1
ALE, idle, powerdown, reset status, A-8, A-9
B
Block diagram
8XC196Lx, 2-2
C
CLKOUT
and internal timing, 2-2–2-4
idle, powerdown, reset status, A-8, A-9
output frequency, 2-5
reset status, 5-2
Clock circuitry, 2-3, 10-2
D
delay register, 8-20
Design considerations, 9-2
Device pin reset status, A-8, A-9
Documents, related, 1-2
E
EA#, idle, powerdown, reset status, A-8, A-9
EPA
interrupt mask 1 register, 7-4
interrupt mask register, 7-4
interrupt pending 1 register, 7-5
interrupt pending register, 7-5
interrupt priority vector register, 7-6
ESD protection, 5-2, 5-5
F
Formulas
clock period (t), 2-4
PH1 and PH2 frequency, 2-4
state time, 2-4
Frequency (f), 2-4
F
XTAL 1
, 2-4
H
Hardware, pin reset status, A-8, A-9
I
Idle mode pin status, A-8, A-9
Internal timing, 2-2, 10-1
Interrupts
mask 1 register, 4-4
mask register, 4-3
pending 1 register, 4-6
pending register, 4-5
priorities, 4-2
sources, 4-2
vectors, 4-2
J
J1850 communications controller, 8-3–8-21
delay compensation, 8-20
in-frame response
command register, 8-17
interrupt status register, 8-21
oscillator prescaler
configuration register, 8-18
receiver register, 8-15
registers, 8-3–8-4
signals, 8-3
transmitter register, 8-14
M
Manual contents, summary, 1-1–1-2
N
Noise, reducing, 5-2
O
ONCE mode, entering and exiting, 10-2
OTPROM address map, 11-1