Inova High Performance CPU board ICP-PII - Manual (Page 88)

©2001 Inova Computers GmbH Page C-6 CPU Appendix-C
IPB-FPE12 Appendix C
C1.5 COM2 Interface
The COM2 port features a complete set of handshaking and modem control signals, maskable
interrupt generation and high-speed data transfer rates. A front-panel with LPT1 and COM2 inter-
faces is either integrated into a 12HP standard CPU front-panel or available as a separate 4HP unit.
The piggyback located behind these interfaces connects to the CPU-mounted J13 connector.
Figure C1.5 COM2 Interface Pinout
1
6
5
9
Table C1.5 COM2 Connector Signals
Note:
The standard piggyback configuration
has COM2 set for RS232 communication.
However, this device can be configured to
observe a two-wire non galvanically
separated RS485 protocol. The data
direction is governed by controlling the
UART’s RTS signal. Writing a hex value of
0B to this register allows data to be
transmitted. Writing 1B to this register
configures the device to receive data.
RS232 RS485
1 DCD
2 RxD RxD, TxD +
3 TxD RxD, TxD -
4 DTR
5 GND
6 DSR
7 RTS
8 CTS
9 RI
Pin No.
Signal