Inova High Performance CPU board ICP-PII - Manual (Page 29)

©2002 Inova Computers GmbH Page 2-5 Doc. PD00581013.004
ICP-PIII Configuration
CompactPCI
®
2
2.2 Memory Mapped Peripherals
PC-AT desktop computers (ISA bus) allow 24-bit memory addressed peripherals. This decoding
permits peripheral boards to be mapped in the Intel 80x86 memory map from 0h to 0FFFFFFh.
Inova’s CompactPCI systems allow the full 32-bit addressing capability of the Intel Pentium/Celeron
range of ‘processors so that memory mapped peripheral devices may be mapped locally to the
‘processor board at any location in the memory map not being used by other devices (e.g. system
RAM.)
The BIOS automatically assigns memory addresses required by peripheral boards and PCI devices
at boot time based on the requirements of each device. The assigned addresses can be deter-
mined by reading the configuration address space registers using PCI software tools.
Note:
Devices not located on the CPU side of
the PCI/PCI bridge are not normally
accessible by DOS.
2.3 Interrupt Routing
The IBM-compatible architecture includes one (PC-XT) or two (PC-AT) programmable interrupt
controllers (Intel 8259A-compatible ‘PICs’) configured to set the priority of interrupt requests to
the CPU.
In the PC-AT architecture, one PIC is programmed as the ‘master’ with one input (IRQ2) being the
‘cascaded’ interrupt from the second ‘slave’ PIC.
This configuration allows for a total of 15 interrupt sources to the CPU. Table 2.3 shows the
interrupts with their corresponding vectors and sources as defined for AT PCs.
Note:
*) Denotes Plug ‘n’ Play devices that
are configured during the BSP POST.
Values shown are ISA compatible I/O
addresses for reference only.