Inova High Performance CPU board ICP-PII - Manual (Page 41)

©2002 Inova Computers GmbH Page 3-7 Doc. PD00581013.004
ICP-PIII Interfaces
CompactPCI
®
3
Table 3.05 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (B)
1) : 5V TTL signals from serial I/O controller
2) : Termination of USB lines on CPU. The +5V and GND signals need fuses and inductors for
decoupling (USB specification).
3) : The 5V LPT signals need decoupling and pull-up resistors near the backplane LPT␣ 1
connector.
4) : 5V open collector signal (5V/100mA)
5) : Option “External Battery” (Note: battery must be removed from CPU board)
U
bat
= +3.4V to +3.6V
6) : RS485 signals
Pin Nr Row A Row B Row C Row D Row E
J2-22 - - - - -
J2-21 CLK6 GND ETH_TxF+ ETH_TxF- ETH_R45
J2-20 CLK5 GND - GND ETH_R78
J2-19 GND GND - ETH_RxF+ ETH_RxF-
J2-18 LPT-STP 3) LPT-PE 3) - GND -
J2-17 LPT-AFD 3) GND PRST# REQ6# GNT6#
J2-16 LPT-D0 3) LPT-ACK 3) USB1-DATA+ 2) GND (UBAT) 5)
J2-15 LPT-ERR 3) GND USB1-DATA- 2) REQ5# GNT5#
J2-14 LPT-D1 3) LPT-SLCT 3) H5V(1A) GND RI1 1)
J2-13 LPT-INIT 3) GND V(I/O) DTR1 1) CTS1 1)
J2-12 LPT-D2 3) - USB2-DATA+ 2) GND TxD1 1)
J2-11 LPT-SLIN 3) GND V(I/O) RTS1 1) RxD1 1)
J2-10 LPT-D3 3) - USB2-DATA- 2) GND DSR1 1)
J2-09 LPT-D4 3) GND V(I/O) DCD1 1) RI2 1)
J2-08 LPT-D5 3) - - GND DTR2 1)
J2-07 LPT-BUSY 3) GND V(I/O) CTS2 1) TxD2 1)
J2-06 LPT-D6 3) - - GND RTS2 1)
J2-05 LPT-D7 3) GND V(I/O) RxD2 1) DSR2 1)
J2-04 V(I/O) SPEAKER 4) - GND DCD2 1)
J2-03 CLK4 GND GNT3# REQ4# GNT4#
J2-02 CLK2 CLK3 SYSEN# GNT2# GNT3#
J2-01 CLK1 GND REQ1# GNT1# REQ2#