Inova High Performance CPU board ICP-PII - Manual (Page 35)

©2002 Inova Computers GmbH Page 3-1 Doc. PD00581013.004
ICP-PIII Interfaces
CompactPCI
®
3
Interfaces
Interfaces Contents
3.0 CompactPCI J1/J2 Connector ... 3-3
3.01 CompactPCI Connector ........................................................................... 3-3
Figure 3.01 The 32-Bit CompactPCI Bus Interface Connector ...................................................... 3-3
3.02 ICP-PIII Connector J1 and J2 ..................................................................... 3-3
Table 3.02 Inova’s ICP-PIII 32-Bit CompactPCI J1 Pin Assignment ............................................... 3-4
Table 3.03 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment (Standard) ............................ 3-5
Table 3.04 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (A) ..................... 3-6
Table 3.05 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (B) ...................... 3-7
Table 3.06 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (C) ..................... 3-8
Table 3.07 Inova’s ICP-PIII Rear I/O J2 (CPU) Integration .......................................................... 3-9
3.1 CompactPCI Backplane .......... 3-10
Figure 3.10 Inova’s 32-Bit CompactPCI 8-Slot Backplane - RH System Slot ................................ 3-11
3.2 Interfaces ............................. 3-12
3.21 J7 & J12 Fast Ethernet ............................................................................ 3-12
Figure 3.21 RJ45 Pinout ........................................................................................................... 3-12
Table 3.21 Ethernet Connector Signals ..................................................................................... 3-12
3.22 J17 VGA Interface ................................................................................... 3-13
Figure 3.22 High-Density D-Sub VGA Interface Pinout .............................................................. 3-13
Table 3.22 Video Output Connector Signals ............................................................................. 3-13
Table 3.22b Video Resolutions ................................................................................................. 3-14
3.23 J16 PanelLink Interface ........................................................................... 3-15
Figure 3.23 PanelLink Interface Connector ............................................................................... 3-15
Table 2.12 PanelLink Interface ................................................................................................. 3-15
2.24 J16 GigaSTAR Interface ........................................................................... 3-16
Figure 2.24 GigaSTAR D-Sub Interface Pinout ........................................................................... 3-16
Table 2.11 GigaSTAR Interface ................................................................................................ 3-16
3.25 J19 USB Interface ................................................................................... 3-17
Figure 3.25 USB Interface Pinout .............................................................................................. 3-17
Table 3.25 USB Connector Signals ........................................................................................... 3-17
3.26 J15 FireWire Interface ............................................................................. 3-18
Figure 3.26 FireWire Interface Pinout ........................................................................................ 3-18
Table 3.26 FireWire Connector Signals ..................................................................................... 3-18
3.27 J20 Infrared (iRdA) Interface ................................................................... 3-19
3.28 J20 Reset Button..................................................................................... 3-19