Avago Technologies LSI53C120 - Manual (Page 63)

Index IX-3
R
RC-type input filters 2-3
Receiver B-6
Receiver latch 2-6
Reconnect B-6
Recovery 2-8
Release B-6
Reliability issue 2-3
REQ 2-7, B-6
Request 2-3
Request (REQ) 2-7
Reselect B-6
Reserved B-6
RESET 2-10, B-6
Reset (RST) 2-7
RESET/ 3-7
RESET/ Control Signal Polarity 2-10
Re-timing 2-7
Re-timing circuit 2-1
Re-timing logic block 2-3
RST B-6
S
Scalable device connectivity 1-4
SCAM support 2-9
SCSI B-7
TolerANT technology 2-3
SCSI A Signal Description 3-4
SCSI Address B-6
SCSI A-side 1-4, 2-4
SCSI B-side 1-4, 2-4
SCSI bus disable mode 1-3, 1-4
SCSI bus electrical isolation 1-3, 1-6
SCSI bus protocol 2-4, 2-9
SCSI Device ID B-6
SCSI I/O logic 2-8
SCSI ID 1-3, B-6
SCSI Interface Timings 3-16
SCSI phases 2-3
SCSI Signals 3-10
SEL B-7
Signal groupings 2-4
Signal skew 2-2
Single-ended configuration B-7
Single-ended control blocks 2-1, 2-2
Single-ended to differential 1-3, 1-5, 2-4
Single-ended to single-ended 1-3, 1-5, 2-2
Software 1-3, 2-1
Source bus 2-2, 2-5
State 2-8
State machines 2-7
State-machine control 2-1
State-machine controls 2-3, 2-4
Storage temperature 3-8
Supply voltage 3-8
SYM53C120 Pin Diagram 3-1
SYM53C120 SCSI Buddy 1-1
Synchronous 1-3
Synchronous transmission B-7
T
Target B-7
Temperature 2-3
Termination B-7
Thermal resistance 3-9
TolerANT receiver technology 2-3
TolerANT SCSI 2-3
TolerANT Technology 2-3
Benefits 2-3
Electrical characteristics 3-12
TolerANT® Drivers and Receivers 2-1, 2-3
TolerANT® technology 2-3
Typical applications 1-4
U
Ultra SCSI bus 1-4
V
VDD_CORE 3-7
VDD_IO 3-7
VDD-SCSI 3-7
Vendor unique B-7
Voltage 2-3
VSS_CORE 3-7
VSS_IO 3-7
VSS-SCSI 3-7
W
Warm Start Enable and Transfer Active (WS_ENABLE and
XFER_ACTIVE) 2-10
Wide Ultra SCSI 1-3, 2-2
WS_ENABLE 3-7
WS_ENABLE Signal Polarity 2-11
X
XFER_ACTIVE 3-7
XFER_ACTIVE Signal Polarity 2-11