Avago Technologies LSI53C120 - Manual (Page 61)

LSI53C120 Ultra SCSI Bus Expander IX-1
Index
Symbols
sB-7
Numerics
3-state 2-6
3-state leakage 3-9
A
A_SACK/ 2-7, 3-4
A_SATN/ 2-8, 3-4
A_SBSY/ 2-6, 3-4
A_SCD/ 2-8, 3-4
A_SD/(15-0) 3-4
A_SDP/(1-0) 3-4
A_SIO/ 3-4
A_SMSG/ 2-8, 3-4
A_SREQ/ 2-7, 3-4
A_SRST/ 2-7, 3-4
A_SSEL/ 3-4
Absolute Maximum Stress Ratings 3-8
AC characteristics 3-15
ACK 2-7, B-1
Acknowledge 2-3
Acknowledge (ACK) 2-7
Active negation 2-3
ANSI B-1
Application examples 1-4
Arbitration B-1
Asserted B-1
Assertion B-1
Asynchronous 1-3
Asynchronous transmission B-1
ATN B-1
Attention 3-4, 3-5
Attention (ATN) 2-8
B
B_ACKDIR 2-8, 3-6
B_ATNDIR 2-8, 3-6
B_BSYDIR 2-8, 3-6
B_CD_DIR 2-8, 3-6
B_IO_DIR 2-8, 3-6
B_MSGDIR 2-8, 3-6
B_REQDIR 2-8, 3-6
B_RSTDIR 2-8, 3-6
B_SACK/ 2-7, 3-5
B_SATN/ 2-8, 3-5
B_SBSY/ 2-6, 3-5
B_SCD/ 2-8, 3-5
B_SD/(15-0) 3-5
B_SDIR(15-0) 3-6
B_SDIR(15-0, P0, P1) 2-8
B_SDIRP(1-0) 3-6
B_SDP/(1-0) 3-5
B_SELDIR 2-8, 3-6
B_SIO/ 2-8, 3-5
B_SMSG/ 2-8, 3-5
B_SREQ/ 2-7, 3-5
B_SRST/ 2-7, 3-5
B_SSEL/ 3-5
Balanced duty cycles 2-3
Bi-directional connections 2-2
Block B-1
BSY B-1
Bus B-2
Bus arbitration 3-4, 3-5
Bus Reset 3-5
Bus timings 2-4
Busy (BSY) 2-6
C
C_D B-2
Calibration 2-3
Capacitance 3-10
Card Information Structure B-2
CCS B-2
Chip Reset (RESET/) 2-10
CLOCK 3-7
Clock (CLOCK) 2-11
Clock signal 2-6
Clock Timing 3-15
Configuration 1-5, 1-6
Configurations 1-4
Connect B-2
Control Signals 3-11, B-2
Control/Data (C/D) 2-8
Controller B-2
D
D0-D7 B-2
Data 2-3, 2-5, 3-5
Data handshake 3-4, 3-5
Data parity bits 3-5
DB0-DB7 B-2
DC Characteristics 3-8
De-asserted B-2