Avago Technologies LSI53C120 - Manual (Page 24)

2-6 Functional Description
LSI53C120 can be the source bus or the load bus. The side asserting,
deasserting, or releasing the SCSI signals is the source side. The
following steps are a part of the LSI53C120 data path.
1. The receiver logic accepts the asserted data as soon as it is
received. Once the clock signal (REQ/ACK) has been received, then
the receiver latch gates the data.
2. The path is tested to ensure the signal if being driven by the
LSI53C120 is not misinterpreted as an incoming signal.
3. The data is leading edge filtered. The assertion edge is held for a
specified time to prevent any signal bounce. The input signal controls
the duration.
4. A latch samples the signal. This provides a stable data window for
the load bus.
5. The final stage develops pull-up and pull-down controls for the SCSI
I/O logic, including 3-state controls for the pull-up.
6. A parallel function ensures that bus (transmission line) recovery is
ensured for a specified time after the last signal deassertion on each
signal line.
2.2.2 Busy (BSY) Control
The LSI53C120 propagates the A_SBSY/ and B_SBSY/ signals from the
source bus to the load bus. The following steps describe this process.
1. The bus is tested to ensure the signal if being driven by the
LSI53C120 is not misinterpreted as an incoming signal.
2. The data is leading edge filtered. The assertion edge is held for a
specified time to prevent any signal bounce. The input signal controls
the duration.
3. The signal path switches the long and short filters used in the circuit
depending upon the current state of the LSI53C120. The current
state of the LSI53C120 State Machine that tracks SCSI phases
selects the mode. The short filter mode passes data through, while
the long filter mode indicates the bus free state. When the Busy
(SBSY) and Select (SSEL) sources switch from side to side, the long
filter mode is used. This output is then fed to the output driver, which
is a pull-down open collector only.