Avago Technologies LSI53C120 - Manual (Page 25)

SCSI Signal Descriptions 2-7
4. A parallel function ensures that bus (transmission line) recovery is
ensured for a specified time after the last signal deassertion on each
signal line.
2.2.3 Reset (RST) Control
The LSI53C120 passes A_SRST/ and B_SRST/ reset signals from the
source to the load bus. The following steps describe this process.
1. The LSI53C120 blocks another RST input signal if one is already
being driven from the source to the load bus.
2. The next stage is a leading edge filter. This ensures that the output
does not switch for a specified time after the leading edge. The
duration of the input signal then determines the duration of the
output.
3. A parallel function ensures that bus (transmission line) recovery is
ensured for a specified time after the last signal deassertion on each
signal line.
2.2.4 Request (REQ)/Acknowledge (ACK) Control
A_SACK/, B_SACK/, A_SREQ/ and B_SREQ/ are clock and control
signals. Their signal paths contain controls to guarantee minimum pulse
width, filter edges, and does some re-timing when used as data transfer
clocks. Each signal, REQ and ACK, has paths from A to B and B to A.
The received signal goes through the following processing steps before
being sent to the opposite bus.
1. The asserted input signal is sensed and forwarded to the next stage
if the direction control permits it. The direction controls are developed
from state machines that are driven by the sequence of bus control
signals.
2. The signal must then pass the test of not being generated by the
LSI53C120.
3. The next stage is a leading edge filter. This ensures that the output
does not switch during the specified hold time after the leading edge.
The duration of the input signal determines the duration of the output
after the hold time. The circuit guarantees a minimum pulse.
4. The next stage passes the signal if it is not a data clock. If REQ or
ACK is a data clock, it delays the leading edge to improve data