Avago Technologies LSI53C120 - Manual (Page 29)

SCSI Signal Descriptions 2-11
that the LSI53C120 no longer passes through signals until the
WS_ENABLE/ pin is deasserted HIGH and both SCSI buses enter the
Bus Free state. As an indication that the chip is idle, or ready to be warm
swapped, the XFER_ACTIVE signal deasserts LOW. An LED or some
other indicator could be connected to the XFER_ACTIVE signal. LSI
Logic recommends using the Warm Swap Enable feature to isolate
buses for specific situations.
2.2.9.3 Transfer Active (XFER_ACTIVE)
This output is an indication that the chip has finished its internal testing,
the SCSI bus has entered a Bus Free state, and SCSI traffic can no pass
from one bus to the other. The signal is asserted HIGH when the chip is
active.
2.2.9.4 Clock (CLOCK)
This is the 40 MHz oscillator input to the LSI53C120. This is the clock
source for protocol control state machines and timing generation logic.
This clock is not used in any bus signal transfer paths.
Table 2.5 WS_ENABLE/ Signal Polarity
Signal Level State Effect
LOW = 0 Asserted The LSI53C120 is requested to go off-line
after detection of a SCSI Bus Free state
HIGH = 1 Deasserted The LSI53C120 is enabled to run normally.
Table 2.6 XFER_ACTIVE Signal Polarity
Signal Level State Effect
HIGH = 1 Asserted Indicates normal operation, and transfers
through the LSI53C120 are enabled
LOW = 0 Deasserted The LSI53C120 has detected a Bus Free
state due to WS_ENABLE/ being LOW,
thus disabling transfers through the
device.