Avago Technologies LSI53C120 - Manual (Page 11)

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Tables
1.1 Modes of Operation 1-1
2.1 Direction Control Signals (B_SDIR(15-0, P0, P1), B_BSYDIR,
B_SELDIR, B_CD_DIR, B_IO_DIR, B_MSGDIR, B_REQDIR,
B_ACKDIR, B_ATNDIR and B_RSTDIR) Polarities
2-9
2.2 DIFF_MODE/ Control Signal Polarity 2-9
2.3 DIFF_SENSE Control Signal Polarity 2-10
2.4 RESET/ Control Signal Polarity 2-10
2.5 WS_ENABLE/ Signal Polarity 2-11
2.6 XFER_ACTIVE Signal Polarity 2-11
3.1 SCSI A Signal Description 3-4
3.2 SCSI B Signal Description 3-5
3.3 SCSI B Differential Signal Description 3-6
3.4 Chip Control Signal Description 3-7
3.5 SCSI Control Signal Description 3-7
3.6 Power and Ground Signal Description 3-7
3.7 No Connect Pins 3-8
3.8 Absolute Maximum Stress Ratings 3-8
3.9 Operating Conditions 3-9
3.10 SCSI Signals – A_SD(15-0)/, A_SDP(1-0)/, A_SREQ/,
A_SACK/, B_SD(15-0)/, B_SDP(1-0)/, B_SREQ/, B_SACK/
3-9
3.11 SCSI Signals – A_SMSG, A_SI_O/, A_SC_D/, A_SATN/,
A_SBSY/, A_SSEL/, A_SRST/, B_SMSG, B_SI_O/,
B_SC_D/, B_SATN/, B_SBSY/, B_SSEL/, B_SRST/
3-10
3.12 Input Signals – CLOCK, DIFF_SENSE, DIFF_MODE/*,
WS_ENABLE/*
3-10
3.13 Capacitance 3-10
3.14 Differential Signals - B_SDIR(15-0), B_SDIRP0, B_SDIRP1,
B_CD_DIR, B_IO_DIR, B_MSGDIR, B_REQDIR,
B_B_ACKDIR, B_BSYDIR, B_SELDIR, B_RSTDIR
3-11
3.15 Control Signals - RESET/ 3-11
3.16 Control Signals - XFER_ACTIVE 3-11
3.17 TolerANT Technology Electrical Characteristics 3-12
3.18 Clock Timing 3-15
3.19 Input Timing 3-16
3.20 Output Timing 3-16