Avago Technologies LSI53C120 - Manual (Page 62)

IX-2 Index
Decoupling capacitor 3-1, 3-3
Delay settings 2-3
Device B-2
DIFF_MODE 3-7
Diff_Mode Control Signal Polarity 2-9
DIFF_SENSE 3-7
Diff_Sense 3-7
Diff_Sense Control Signal Polarity 2-10
Differential control 2-1
Differential Direction Controls 2-8
Differential Mode (Diff_Mode) 2-9
Differential Sense (Diff_Sense) 2-9
Differential Signals 3-11
Disconnect B-2
Double clocking of data 2-3
Driver B-2
Driver direction control 3-6
E
EEPROM B-3
Electrostatic discharge 3-8
Enable/disable SCSI transfers 3-7
ESD 3-8
External differential transceiver 2-8
External SCSI bus 1-6
F
Filter edges 2-7
Free B-3
G
Gigabyte B-3
Glitches 2-3
H
High (logical level) B-3
Host B-3
Host Adapter B-3
Hysteresis 2-5
I
I/O B-3
I/O Cycle B-4
I/O Mapped B-4
Identification B-6
Initiator B-3
Input and Output Timings 3-16
Input capacitance of I/O pads 3-10
Input capacitance of input pads 3-10
Input high voltage 3-9
Input low voltage 3-9
Input Signals 3-10
Input Voltage 3-8
Input/Output (I/O) 2-8
Internal SCSI bus 1-6
Internal split ground system 3-1
IREQ B-4
L
Latch-up current 3-8
LBA B-4
Leading edge filter 2-7
Leading edge filtered 2-6
Lload bus 2-2
Load bus 2-5
Logical Block Address B-4
Logical Unit B-4
Low (logical level) B-4
LSB B-4
LUN B-4
M
Mandatory B-4
Master reset 3-7
Memory Cycle B-4
Memory Interface B-4
Memory Mapped B-5
Message (MSG) 2-8
MHz B-5
microsecond B-5
MSB B-5
MSG B-5
N
nanosecond B-5
Negated B-5
Negation B-5
ns B-5
O
Operating Conditions 3-9
Operating free air 3-9
Output high voltage 3-9
Output low voltage 3-9
P
Parallel function 2-7
Parity 2-3, 2-5, B-5
PC B-5
Peripheral device B-6
Phase B-6
Phase line 3-4, 3-5
Plastic Quad Flat Pack (PQFP) 3-1, 3-4, 3-5, 3-6
Port B-6
Power On Reset (POR) 2-10
Power-down 2-3
Power-up 2-3
Precision delay control 2-1
Precision delay control block 2-3
Precision delay elements 2-3
Priority B-6
Protocol B-6
Pull-down 2-6, 2-8
Pull-up 2-6, 2-8
Pulse width 2-7