Measurement Computing DaqBook 2000 Series - Manual (Page 20)

2-4 Device Overviews 898095 DaqBook/2000 Series and DaqOEM/2000 Series
Digital Input Channels
The devices allow for either synchronous scanning of digital input channels or asynchronous I/O
operations for all configured digital channels.
Counter Input Channels
The DaqBook/2000 Series and DaqOEM/2000 Series devices allow for synchronous scanning of the 4
16-bit counter input channels. The four 16-bit counter channels can also be cascaded into two 32-bit
counter channels. For either cascaded or non-cascaded counter channels each channel can be configured
for:
• Pulse Counting Mode
– specifies that each counter should be cleared upon being read and placed into
the input scan.
• Totalize Counting Mode – specifies that each counter is to free-run and not be cleared during the input
acquisition.
Synchronous Input Acquisition Clocking
The DaqBook/2000 Series and DaqOEM/2000 Series devices allow clocking of the synchronized inputs
either by an internal, programmable pacer clock or by external clocking. These products use a sequencer
to implement a multiplexing approach to gathering the input data. This means that with either internal or
external clocking the entire channel scan (including the sampling time for each channel) may not exceed
the maximum aggregate rate of 200 kHz.
Synchronous Output Operations
The DaqBook/2001, DaqBook/2020, and DaqOEM/2001 allow for synchronous output of D/A channels at
up to 100 kHz for each channel. All D/A channels can output waveform data from an on-board 256 k
sample buffer.
Output Channel Configuration
Analog Output Channels
For DaqBook/2001, DaqBook/2020, and DaqOEM/200, each D/A channel can be configured for
waveform output individually. If the D/A channel is not configured for waveform output it then is
available for asynchronous output operations.
Digital Output Channel
May only be used for asynchronous digital I/O operations.
Synchronous Output Clocking
The DaqBook/2000 Series and DaqOEM/2000 Series devices allow clocking of the synchronized output by
the acquisition clock source, an internal, programmable pacer clock or by an external clock source. When
the clock source generates a new clock signal all outputs are updated concurrently. Regardless of the clock
source, the clock may not exceed the maximum update rate of 100 kHz.
Synchronous Output Data Source for DACs
For DaqBook/2001, DaqBook/2020, and DaqOEM/2001, the data source for synchronized output
operations can be that of the on-board 256k sample buffer.